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OpenFPGA/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf

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add implicit verilog test case to Travis CI
2020-04-12 21:00:20 -05:00
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
[Test] Bug fix in counter micro benchmark tests
2021-06-22 17:33:50 -05:00
power_analysis = false
add implicit verilog test case to Travis CI
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spice_output=false
verilog_output=true
[Test] Update counter test case for cover most counter HDL design
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timeout_each_job = 5*60
fpga_flow=yosys_vpr
update task files using the new syntax on SHELL variables
2020-07-27 16:25:49 -05:00
[OpenFPGA_SHELL]
[Test] Use preconfigured testbench template to run counter8 tests
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
[Test] Bug fix in counter micro benchmark tests
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
[Test] Update counter test case for cover most counter HDL design
2021-06-21 19:13:18 -05:00
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
add implicit verilog test case to Travis CI
2020-04-12 21:00:20 -05:00
[ARCHITECTURES]
[Test] Bug fix in counter micro benchmark tests
2021-06-22 17:33:50 -05:00
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
add implicit verilog test case to Travis CI
2020-04-12 21:00:20 -05:00
[BENCHMARKS]
[Test] Update all the tasks that use counter benchmark
2021-07-02 18:29:13 -05:00
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
[Test] Add dedicated pin constraints for counter designs
2022-02-14 15:54:48 -06:00
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
add implicit verilog test case to Travis CI
2020-04-12 21:00:20 -05:00
[SYNTHESIS_PARAM]
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
2022-01-20 15:21:00 -06:00
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
bench_yosys_bram_map_rules_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
bench_yosys_bram_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 02:21:29 -06:00
bench_read_verilog_options_common = -nolatches
[Test] Bug fix
2021-10-30 18:00:47 -05:00
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
2022-02-14 15:15:55 -06:00
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
[Test] Update counter test case for cover most counter HDL design
2021-06-21 19:13:18 -05:00
start using counter benchmark in regression tests
2020-05-31 20:52:18 -05:00
bench0_top = counter
[Test] Update pin constraints for different counter benchmarks
2022-02-14 17:28:03 -06:00
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_rst.xml
[Test] Add dedicated pin constraints for counter designs
2022-02-14 15:54:48 -06:00
[Test] Update counter test case for cover most counter HDL design
2021-06-21 19:13:18 -05:00
bench1_top = counter
[Test] Add dedicated pin constraints for counter designs
2022-02-14 15:54:48 -06:00
bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench2_top = counter
bench2_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_resetb.xml
add implicit verilog test case to Travis CI
2020-04-12 21:00:20 -05:00
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
[Test] Truncating counter designs in each task
2022-02-14 14:22:19 -06:00
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=