tangxifan
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7ef808cbe4
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[Test] Update pin constraints for different counter benchmarks
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2022-02-14 15:28:03 -08:00 |
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tangxifan
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570c1b10dc
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[Test] Add dedicated pin constraints for counter designs
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2022-02-14 13:54:48 -08:00 |
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tangxifan
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85011824e2
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[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
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2022-02-14 13:15:55 -08:00 |
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tangxifan
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6630c17c23
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[Test] Use preconfigured testbench template to run counter8 tests
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2022-02-14 13:07:31 -08:00 |
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tangxifan
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da3f9ccb80
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[Test] Truncating counter designs in each task
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2022-02-14 12:22:19 -08:00 |
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tangxifan
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0268814fc6
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[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
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2022-02-14 12:20:56 -08:00 |