2020-02-12 20:45:14 -06:00
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/********************************************************************
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* This file includes all the reserved words that are used in
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* naming module, blocks, instances and cells in FPGA X2P support,
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* including:
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* Verilog generation, SPICE generation and bitstream generation
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*******************************************************************/
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#ifndef OPENFPGA_RESERVED_WORDS_H
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#define OPENFPGA_RESERVED_WORDS_H
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2020-02-12 21:25:05 -06:00
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/* begin namespace openfpga */
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namespace openfpga {
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2020-02-13 16:27:16 -06:00
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/* IO PORT */
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/* Prefix of global input, output and inout ports of FPGA fabric */
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constexpr char* GIO_INOUT_PREFIX = "gfpga_pad_";
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2020-02-12 21:25:05 -06:00
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2020-02-12 20:45:14 -06:00
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/* Grid naming constant strings */
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constexpr char* GRID_MODULE_NAME_PREFIX = "grid_";
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2020-02-13 16:27:16 -06:00
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constexpr char* LOGICAL_MODULE_NAME_PREFIX = "logical_tile_";
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2020-02-12 20:45:14 -06:00
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/* Memory naming constant strings */
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constexpr char* GRID_MEM_INSTANCE_PREFIX = "mem_";
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constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
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constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
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constexpr char* MEMORY_MODULE_POSTFIX = "_mem";
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/* Multiplexer naming constant strings */
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constexpr char* MUX_BASIS_MODULE_POSTFIX = "_basis";
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constexpr char* GRID_MUX_INSTANCE_PREFIX = "mux_";
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constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
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constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
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/* Bitstream file strings */
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constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";
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2020-02-12 21:25:05 -06:00
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} /* end namespace openfpga */
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2020-02-12 20:45:14 -06:00
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#endif
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