OpenFPGA/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif

# Benchmark pipelined_32b_adder
.model pipelined_32b_adder
.inputs clk wen ren raddr_0_ raddr_1_ raddr_2_ raddr_3_ raddr_4_ raddr_5_ waddr_0_ waddr_1_ waddr_2_ waddr_3_ waddr_4_ waddr_5_ a_0_ a_1_ a_2_ a_3_ a_4_ a_5_ a_6_ b_0_ b_1_ b_2_ b_3_ b_4_ b_5_ b_6_
.outputs q_0_ q_1_ q_2_ q_3_ q_4_ q_5_ q_6_ q_7_

# Start pipeline
# Pipeline a
.subckt shift D=a_0_ clk=clk Q=a_st0_0_
.subckt shift D=a_st0_0_ clk=clk Q=a_st1_0_
.subckt shift D=a_1_ clk=clk Q=a_st0_1_
.subckt shift D=a_st0_1_ clk=clk Q=a_st1_1_
.subckt shift D=a_2_ clk=clk Q=a_st0_2_
.subckt shift D=a_st0_2_ clk=clk Q=a_st1_2_
.subckt shift D=a_3_ clk=clk Q=a_st0_3_
.subckt shift D=a_st0_3_ clk=clk Q=a_st1_3_
.subckt shift D=a_4_ clk=clk Q=a_st0_4_
.subckt shift D=a_st0_4_ clk=clk Q=a_st1_4_
.subckt shift D=a_5_ clk=clk Q=a_st0_5_
.subckt shift D=a_st0_5_ clk=clk Q=a_st1_5_
.subckt shift D=a_6_ clk=clk Q=a_st0_6_
.subckt shift D=a_st0_6_ clk=clk Q=a_st1_6_

# Pipeline b
.subckt shift D=b_0_ clk=clk Q=b_st0_0_
.subckt shift D=b_st0_0_ clk=clk Q=b_st1_0_
.subckt shift D=b_1_ clk=clk Q=b_st0_1_
.subckt shift D=b_st0_1_ clk=clk Q=b_st1_1_
.subckt shift D=b_2_ clk=clk Q=b_st0_2_
.subckt shift D=b_st0_2_ clk=clk Q=b_st1_2_
.subckt shift D=b_3_ clk=clk Q=b_st0_3_
.subckt shift D=b_st0_3_ clk=clk Q=b_st1_3_
.subckt shift D=b_4_ clk=clk Q=b_st0_4_
.subckt shift D=b_st0_4_ clk=clk Q=b_st1_4_
.subckt shift D=b_5_ clk=clk Q=b_st0_5_
.subckt shift D=b_st0_5_ clk=clk Q=b_st1_5_
.subckt shift D=b_6_ clk=clk Q=b_st0_6_
.subckt shift D=b_st0_6_ clk=clk Q=b_st1_6_

# Pipeline waddr
.subckt shift D=waddr_0_ clk=clk Q=waddr_st0_0_
.subckt shift D=waddr_st0_0_ clk=clk Q=waddr_st1_0_
.subckt shift D=waddr_1_ clk=clk Q=waddr_st0_1_
.subckt shift D=waddr_st0_1_ clk=clk Q=waddr_st1_1_
.subckt shift D=waddr_2_ clk=clk Q=waddr_st0_2_
.subckt shift D=waddr_st0_2_ clk=clk Q=waddr_st1_2_
.subckt shift D=waddr_3_ clk=clk Q=waddr_st0_3_
.subckt shift D=waddr_st0_3_ clk=clk Q=waddr_st1_3_
.subckt shift D=waddr_4_ clk=clk Q=waddr_st0_4_
.subckt shift D=waddr_st0_4_ clk=clk Q=waddr_st1_4_
.subckt shift D=waddr_5_ clk=clk Q=waddr_st0_5_
.subckt shift D=waddr_st0_5_ clk=clk Q=waddr_st1_5_
# Pipeline wen
.subckt shift D=wen clk=clk Q=wen_st0
.subckt shift D=wen_st0 clk=clk Q=wen_st1
# End pipeline

# Start adder
.subckt adder a=a_st1_0_ b=b_st1_0_ cin=zero00 cout=cint01 sumout=AplusB_0_
.subckt adder a=a_st1_1_ b=b_st1_1_ cin=cint01 cout=cint02 sumout=AplusB_1_
.subckt adder a=a_st1_2_ b=b_st1_2_ cin=cint02 cout=cint03 sumout=AplusB_2_
.subckt adder a=a_st1_3_ b=b_st1_3_ cin=cint03 cout=cint04 sumout=AplusB_3_
.subckt adder a=a_st1_4_ b=b_st1_4_ cin=cint04 cout=cint05 sumout=AplusB_4_
.subckt adder a=a_st1_5_ b=b_st1_5_ cin=cint05 cout=cint06 sumout=AplusB_5_
.subckt adder a=a_st1_6_ b=b_st1_6_ cin=cint06 cout=cint07 sumout=AplusB_6_
.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB_7_
# End adder

# Start DPRAM
.subckt dual_port_ram_32x512 clk=clk wen=wen_st1 ren=ren \
waddr[0]=waddr_st1_0_ waddr[1]=waddr_st1_1_ waddr[2]=waddr_st1_2_ waddr[3]=waddr_st1_3_ waddr[4]=waddr_st1_4_ \
waddr[5]=waddr_st1_5_ waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 \
raddr[0]=raddr_0_ raddr[1]=raddr_1_ raddr[2]=raddr_2_ raddr[3]=raddr_3_ raddr[4]=raddr_4_ raddr[5]=raddr_5_ \
raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 \
d_in[0]=AplusB_0_ d_in[1]=AplusB_1_ d_in[2]=AplusB_2_ d_in[3]=AplusB_3_ d_in[4]=AplusB_4_ d_in[5]=AplusB_5_ \
d_in[6]=AplusB_6_ d_in[7]=AplusB_7_ d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \
d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \
d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \
d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \
d_in[30]=zero00 d_in[31]=zero00 \
d_out[0]=q_0_ d_out[1]=q_1_ d_out[2]=q_2_ d_out[3]=q_3_ d_out[4]=q_4_ d_out[5]=q_5_ \
d_out[6]=q_6_ d_out[7]=q_7_ d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \
d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \
d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \
d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \
d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=unconn d_out[31]=unconn 
# End DPRAM

# Start global variable
.names zero00
0
# End global variable


.end

# Start blackbox definition
.model dual_port_ram_32x512
.inputs clk ren wen waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \
 waddr[6] waddr[7] waddr[8] raddr[0] raddr[1] raddr[2] \
 raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] \
 d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \
 d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \
 d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \
 d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31]
.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \
 d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \
 d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \
 d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \
 d_out[28] d_out[29] d_out[30] d_out[31]
.blackbox
.end


.model adder
.inputs a b cin
.outputs cout sumout
.blackbox
.end


.model shift
.inputs D clk
.outputs Q
.blackbox
.end
# End blackbox definition