42 lines
849 B
Plaintext
42 lines
849 B
Plaintext
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# Yosys synthesis script for alu4
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# read Verilog
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read_verilog /full_path/design.v #can be repeated if project has many files
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read_verilog -lib /full_path/cells_sim.v # file we provide
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hierarchy -check -top top_module
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proc
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flatten
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tribuf -logic
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synth -run coarse
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opt -fast
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memory -nomap
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opt_clean
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memory_bram -rules /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams.txt
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techmap -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams_map.v
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opt -fast -mux_undef -undriven -fine
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memory_map
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# Technology mapping
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#proc
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techmap -D NO_LUT -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v -map +/adff2dff.v
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# Synthesis
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synth -top top_module -flatten -run fine
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clean
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# LUT mapping
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abc -lut 6
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# Check
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synth -run check
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# Clean and output blif
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opt_clean -purge
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write_blif design.blif
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write_verilog design.v
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