OpenFPGA/docs/source/fpga_verilog/file_organization.rst

Hierarchy of Verilog Output Files
============================

All the generated Verilog Netlists are located in the <verilog_dir> as you specify in the command-line options. Under the <verilog_dir>, FPGA-Verilog creates the top file name_top.v and a number of folders: lb (logic blocks), routing and sub_modules. 

.. csv-table:: Folder hierarchy of FPGA-Verilog
   :header: "Folder", "Content" 
   :widths: 10, 20
    	
   "name_top.v", "Contains the top module and calls all the other .v files"   
   "lb", "Logic Block. Contains all the CLBs. The logic_block.v includes all the CLB and is called by the top module afterward"
   "routing", "Contains all the routing in the circuit. You can find in it the Switch Boxes, the Connection Blocks and the routing needed to connect the different blocks together. The routing.v file packs them all and is called by the top module"
   "sub_modules", "Contains the modules generated by the flow to build the CLBs"
Update file_organization.rst Made similar to the SPICE one 2018-12-03 15:20:34 -06:00			`Hierarchy of Verilog Output Files`
Adding documentation 2018-09-13 16:38:41 -05:00			`============================`
Adds titles and WiP tags for new parts. Tutorials included Added title and WiP tags for comprehension and also to see what is missing and what is going to happen in the near future in the documentation 2018-09-25 15:53:04 -05:00
Update file_organization.rst Made similar to the SPICE one 2018-12-03 15:20:34 -06:00			`All the generated Verilog Netlists are located in the <verilog_dir> as you specify in the command-line options. Under the <verilog_dir>, FPGA-Verilog creates the top file name_top.v and a number of folders: lb (logic blocks), routing and sub_modules.`
FPGA-Verilog_doc_update 2018-10-17 17:38:03 -05:00
Update file_organization.rst Made similar to the SPICE one 2018-12-03 15:20:34 -06:00			`.. csv-table:: Folder hierarchy of FPGA-Verilog`
			`:header: "Folder", "Content"`
			`:widths: 10, 20`

			`"name_top.v", "Contains the top module and calls all the other .v files"`
			`"lb", "Logic Block. Contains all the CLBs. The logic_block.v includes all the CLB and is called by the top module afterward"`
Update file_organization.rst Correction on the routing 2018-12-03 15:21:40 -06:00			`"routing", "Contains all the routing in the circuit. You can find in it the Switch Boxes, the Connection Blocks and the routing needed to connect the different blocks together. The routing.v file packs them all and is called by the top module"`
Update file_organization.rst Made similar to the SPICE one 2018-12-03 15:20:34 -06:00			`"sub_modules", "Contains the modules generated by the flow to build the CLBs"`