2020-10-06 12:56:10 -05:00
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Technical Highlights
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The follow lists of technical features are created to help users spot their needs in customizing FPGA fabrics.(**as of October 2020**)
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Supported Circuit Designs
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~~~~~~~~~~~~~~~~~~~~~~~~~
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2020-10-10 23:40:37 -05:00
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| Circuit Types | Auto-generation | User-Defined | Design Topologies |
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+===============+=================+==============+=====================================================+
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| Inverter | Yes | Yes | - :ref:`circuit_model_power_gated_inverter_example` |
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| | | | - :ref:`circuit_model_inverter_1x_example` |
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| | | | - :ref:`circuit_model_tapered_inv_16x_example` |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| Buffer | Yes | Yes | - :ref:`circuit_model_buffer_2x_example` |
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| | | | - :ref:`circuit_model_power_gated_buffer_example` |
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| | | | - :ref:`circuit_model_tapered_buffer_64x_example` |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| AND gate | Yes | Yes | - :ref:`circuit_model_and2_example` |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| OR gate | Yes | Yes | - :ref:`circuit_model_or2_example` |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| MUX2 gate | Yes | Yes | - :ref:`circuit_model_mux2_gate_example` |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| Pass gate | Yes | Yes | - :ref:`circuit_model_tgate_example` |
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| | | | - :ref:`circuit_model_pass_transistor_example` |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| Look-Up Table | Yes | Yes | - **Any size** |
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| | | | - :ref:`circuit_model_single_output_lut_example` |
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| | | | - :ref:`circuit_model_frac_lut_example` |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| Routing | Yes | No | - **Any size** |
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| Multiplexer | | | - :ref:`circuit_model_mux_multilevel_example` |
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| | | | - :ref:`circuit_model_mux_1level_example` |
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| | | | - :ref:`circuit_model_mux_tree_example` |
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| | | | - :ref:`circuit_model_mux_stdcell_example` |
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| | | | - :ref:`circuit_model_mux_local_encoder_example` |
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| | | | - :ref:`circuit_model_mux_const_input_example` |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| Configurable | No | Yes | - :ref:`circuit_model_config_latch_example` |
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| Memory | | | - :ref:`circuit_model_sram_blwl_example` |
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| | | | - :ref:`circuit_model_dff_example` |
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| | | | - :ref:`circuit_model_ccff_example` |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| Block RAM | No | Yes | - **Any size** |
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| | | | - Single-port |
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| | | | - Dual-port |
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| | | | - Fracturable |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| Arithmetic | No | Yes | - **Any size** |
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| Units | | | - Multiplier |
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| | | | - :ref:`circuit_model_full_adder_example` |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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| I/O | No | Yes | - :ref:`circuit_model_gpio_example` |
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| | | | - Bi-directional buffer |
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| | | | - AIB |
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+---------------+-----------------+--------------+-----------------------------------------------------+
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2020-10-06 12:56:10 -05:00
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* The user defined netlist could come from a standard cell
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Supported FPGA Architectures
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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We support most FPGA architectures that VPR can support!
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The following are most commonly seen architectural features:
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2020-10-10 23:40:37 -05:00
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+------------------------+----------------------------------------------+
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| Block Type | Architecture features |
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+========================+==============================================+
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| Programmable Block | - Single-mode Configurable Logic Block (CLB) |
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| | - Multi-mode Configurable Logic Block (CLB) |
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| | - Single-mode heterogeneous blocks |
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| | - Multi-mode heterogeneous blocks |
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| | - Flexible local routing architecture |
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+------------------------+----------------------------------------------+
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| Routing Block | - Tileable routing architecture |
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| | - Flexible connectivity |
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| | - Flexible Switch Block Patterns |
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+------------------------+----------------------------------------------+
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| | - Chain-based organization |
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| | - Frame-based organization |
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| :ref:`config_protocol` | - Memory bank organization |
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| | - Flatten organization |
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+------------------------+----------------------------------------------+
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2020-10-06 12:56:10 -05:00
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Supported Verilog Modeling
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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OpenFPGA supports the following Verilog features in auto-generated netlists for circuit designs
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- Synthesizable Behavioral Verilog
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- Structural Verilog
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- Implicit/Explicit port mapping
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