2020-10-06 12:56:10 -05:00
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Technical Highlights
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The follow lists of technical features are created to help users spot their needs in customizing FPGA fabrics.(**as of October 2020**)
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Supported Circuit Designs
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~~~~~~~~~~~~~~~~~~~~~~~~~
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+---------------+-----------------+--------------+-------------------------+
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| Circuit Types | Auto-generation | User-Defined | Design Topologies |
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+===============+=================+==============+=========================+
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| Inverter | Yes | Yes | - Power-gating |
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+---------------+-----------------+--------------+-------------------------+
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| Buffer | Yes | Yes | - Tapered buffers |
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| | | | - Power-gating |
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+---------------+-----------------+--------------+-------------------------+
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| AND gate | Yes | Yes | - 2-input |
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+---------------+-----------------+--------------+-------------------------+
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| OR gate | Yes | Yes | - 2-input |
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+---------------+-----------------+--------------+-------------------------+
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| MUX2 gate | Yes | Yes | - 2-input |
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+---------------+-----------------+--------------+-------------------------+
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| Pass gate | Yes | Yes | - Transmission gate |
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| | | | - Pass transistor |
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+---------------+-----------------+--------------+-------------------------+
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| Look-Up Table | Yes | Yes | - **Any size** |
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| | | | - Single-output LUT |
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| | | | - Fracturable LUT |
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| | | | - Buffer location |
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+---------------+-----------------+--------------+-------------------------+
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| Routing | Yes | No | - **Any size** |
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| Multiplexer | | | - Buffer location |
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| | | | - One-level structure |
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2020-10-06 13:00:30 -05:00
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| | | | - Tree structure |
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2020-10-06 12:56:10 -05:00
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| | | | - Multi-level structure |
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| | | | - Local encoders |
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| | | | - Constant inputs |
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+---------------+-----------------+--------------+-------------------------+
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| Configurable | No | Yes | - Latch |
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| Memory | | | - SRAM |
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| | | | - D-type flip-flop |
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+---------------+-----------------+--------------+-------------------------+
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| Block RAM | No | Yes | - Single-port |
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| | | | - Dual-port |
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| | | | - Fracturable |
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| | | | - **Any size** |
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+---------------+-----------------+--------------+-------------------------+
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| Arithmetic | No | Yes | - **Any size** |
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| Units | | | - Multiplier |
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| | | | - Adder |
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+---------------+-----------------+--------------+-------------------------+
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| I/O | No | Yes | - General purpose I/O |
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| | | | - Bi-directional buffer |
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| | | | - AIB |
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+---------------+-----------------+--------------+-------------------------+
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* The user defined netlist could come from a standard cell
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Supported FPGA Architectures
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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We support most FPGA architectures that VPR can support!
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The following are most commonly seen architectural features:
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+--------------------+----------------------------------------------+
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| Block Type | Architecture features |
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+====================+==============================================+
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| Programmable Block | - Single-mode Configurable Logic Block (CLB) |
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| | - Multi-mode Configurable Logic Block (CLB) |
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| | - Single-mode heterogeneous blocks |
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| | - Multi-mode heterogeneous blocks |
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| | - Flexible local routing architecture |
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+--------------------+----------------------------------------------+
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| Routing Block | - Tileable routing architecture |
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| | - Flexible connectivity |
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| | - Flexible Switch Block Patterns |
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+--------------------+----------------------------------------------+
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2020-10-06 13:16:15 -05:00
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| Configuration | - Chain-based organization |
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| Protocol | - Frame-based organization |
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| | - Memory bank organization |
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| | - Flatten organization |
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+--------------------+----------------------------------------------+
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2020-10-06 12:56:10 -05:00
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Supported Verilog Modeling
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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OpenFPGA supports the following Verilog features in auto-generated netlists for circuit designs
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- Synthesizable Behavioral Verilog
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- Structural Verilog
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- Implicit/Explicit port mapping
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