14 lines
219 B
Coq
14 lines
219 B
Coq
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module MAR(
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output reg [3:0] mar_out,
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input wire [3:0] mar_in,
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input lm_,
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input clk,
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input clr_
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);
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always @(posedge clk)
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if(~clr_) mar_out <= 4'b0;
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else if(~lm_) mar_out <= mar_in;
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endmodule
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