2021-09-05 15:23:38 -05:00
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/********************************************************************
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* This file includes functions that are used to organize memories
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* in the top module of FPGA fabric
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*******************************************************************/
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#include <cmath>
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2021-09-05 19:49:01 -05:00
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#include <limits>
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2021-09-05 15:23:38 -05:00
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "vtr_time.h"
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/* Headers from vpr library */
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#include "vpr_utils.h"
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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#include "rr_gsb_utils.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "memory_utils.h"
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#include "decoder_library_utils.h"
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#include "module_manager_utils.h"
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2021-09-05 22:45:56 -05:00
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#include "memory_bank_utils.h"
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2021-09-05 15:23:38 -05:00
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#include "build_decoder_modules.h"
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#include "build_top_module_memory_bank.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/*********************************************************************
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* Top-level function to add nets for quicklogic memory banks
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* Each configuration region has independent memory bank circuitry
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* - Find the number of BLs and WLs required for each region
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* - Create BL and WL decoders, and add them to decoder library
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* - Create nets to connect from top-level module inputs to inputs of decoders
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* - Create nets to connect from outputs of decoders to BL/WL of configurable children
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*
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* Detailed schematic of how memory banks are connected in the top-level:
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* Consider a random Region X, local BL address lines are aligned to the LSB of the
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* top-level BL address lines
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*
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* top_bl_addr[N-1:0]
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* ^
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* | local_bl_addr[N-1:0]
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* |
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* +-----+------------------+
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* | | |
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* | +-------------------+ |
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* | | Word Line Decoder | |
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* | +-------------------+ |
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* | |
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*
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* The BL/WL decoders should have the same circuit designs no matter what region
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* they are placed even when the number of configuration bits are different
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* from one region to another!
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* This is designed to avoid any address collision between memory banks
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* since they are programmed in the same clock cycle
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* For example:
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* - Memory Bank A has 36 memory cells.
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* Its BL decoder has 3 address bit and 6 data output bit
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* Its WL decoder has 3 address bit and 6 data output bit
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* - Memory Bank B has 16 memory cells.
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* Its BL decoder has 2 address bit and 4 data output bit
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* Its WL decoder has 2 address bit and 4 data output bit
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* - If we try to program the 36th memory cell in bank A
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* the BL address will be 3'b110
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* the WL address will be 3'b110
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* the data input will be 1'b0
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* - If we try to program the 4th memory cell in bank A
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* the BL address will be 3'b010
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* the WL address will be 3'b010
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* the data input will be 1'b1
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* However, in both cases, this will trigger a parasitic programming in bank B
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* the BL address will be 2'b10
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* the WL address will be 2'b10
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* Assume the data input is expected to be 1'b1 for bank B
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* but it will be overwritten to 1'b0 when programming the 36th cell in bank A!
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*
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* Detailed schematic of each memory bank:
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* @note The numbers are just made to show a simplified example, practical cases are more complicated!
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*
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* WL_enable WL address
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* | |
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* v v
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* +-----------------------------------------------+
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* | Word Line Decoder |
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* +-----------------------------------------------+
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* +---------+ | | |
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* BL | | | | |
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* enable ---->| |-----------+---------------+---- ... |------+--> BL[0:2]
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* | | | | | | | |
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* | | | v | v | v
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* | Bit | | +-------+ | +-------+ | +------+
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* BL | Line | +-->| SRAM | +-->| SRAM | +->| SRAM |
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* address ---->| Decoder | | | [0:8] | | | [0:5] | ... | | [0:7]|
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* | | | +-------+ | +-------+ | +------+
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* | | | | |
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* | |-----------+--------------+--------- | -----+--> BL[0:9]
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* | | | | | | | |
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* | | | v | v | v
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* | | | +-------+ | +-------+ | +-------+
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* | | +-->| SRAM | | | SRAM | +->| SRAM |
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* | | | | [0:80]| | | [0:63]| ... | | [0:31]|
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* | | | +-------+ | +-------+ | +-------+
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* | | | |
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* | | | ... ... ... | ...
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* | | | | |
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* | |-----------+---------------+---- --- | -----+--> BL[0:3]
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* | | | | | | | |
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* | | | v | v | v
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* | | | +-------+ | +-------+ | +-------+
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* | | +-->| SRAM | +-->| SRAM | +->| SRAM |
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* | | | |[0:5] | | | [0:8] | ... | | [0:2] |
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* | | | +-------+ | +-------+ | +-------+
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* BL | | v v v
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* data_in ---->| | WL[0:9] WL[0:7] WL[0:4]
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* +---------+
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*
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**********************************************************************/
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void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_manager,
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DecoderLibrary& decoder_lib,
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const ModuleId& top_module,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& sram_model,
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const TopModuleNumConfigBits& num_config_bits) {
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/* Find Enable port from the top-level module */
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ModulePortId en_port = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME));
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BasicPort en_port_info = module_manager.module_port(top_module, en_port);
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/* Find data-in port from the top-level module */
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ModulePortId din_port = module_manager.find_module_port(top_module, std::string(DECODER_DATA_IN_PORT_NAME));
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BasicPort din_port_info = module_manager.module_port(top_module, din_port);
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/* Data in port should match the number of configuration regions */
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VTR_ASSERT(din_port_info.get_width() == module_manager.regions(top_module).size());
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2021-09-20 18:05:36 -05:00
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/* Find readback port from the top-level module */
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ModulePortId readback_port = module_manager.find_module_port(top_module, std::string(DECODER_READBACK_PORT_NAME));
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BasicPort readback_port_info;
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/* Readback port if available, should be a 1-bit port */
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if (readback_port) {
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readback_port_info = module_manager.module_port(top_module, readback_port);
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VTR_ASSERT(readback_port_info.get_width() == 1);
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}
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/* Find BL and WL address port from the top-level module */
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ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME));
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BasicPort bl_addr_port_info = module_manager.module_port(top_module, bl_addr_port);
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ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME));
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BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port);
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/* Find the top-level number of BLs and WLs required to access each memory bit */
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size_t bl_addr_size = bl_addr_port_info.get_width();
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size_t wl_addr_size = wl_addr_port_info.get_width();
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/* Each memory bank has a unified number of BL/WLs */
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size_t num_bls = 0;
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for (const auto& curr_config_bits : num_config_bits) {
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num_bls = std::max(num_bls, curr_config_bits.first);
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}
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size_t num_wls = 0;
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for (const auto& curr_config_bits : num_config_bits) {
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num_wls = std::max(num_wls, curr_config_bits.second);
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}
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/* Create separated memory bank circuitry, i.e., BL/WL decoders for each region */
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for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
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/**************************************************************
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* Add the BL decoder module
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* Search the decoder library
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* If we find one, we use the module.
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* Otherwise, we create one and add it to the decoder library
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*/
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DecoderId bl_decoder_id = decoder_lib.find_decoder(bl_addr_size, num_bls,
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true, true, false, false);
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if (DecoderId::INVALID() == bl_decoder_id) {
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bl_decoder_id = decoder_lib.add_decoder(bl_addr_size, num_bls, true, true, false, false);
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}
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VTR_ASSERT(DecoderId::INVALID() != bl_decoder_id);
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/* Create a module if not existed yet */
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std::string bl_decoder_module_name = generate_memory_decoder_with_data_in_subckt_name(bl_addr_size, num_bls);
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ModuleId bl_decoder_module = module_manager.find_module(bl_decoder_module_name);
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if (ModuleId::INVALID() == bl_decoder_module) {
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/* BL decoder has the same ports as the frame-based decoders
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* We reuse it here
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*/
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bl_decoder_module = build_bl_memory_decoder_module(module_manager,
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decoder_lib,
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bl_decoder_id);
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}
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VTR_ASSERT(ModuleId::INVALID() != bl_decoder_module);
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size_t curr_bl_decoder_instance_id = module_manager.num_instance(top_module, bl_decoder_module);
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module_manager.add_child_module(top_module, bl_decoder_module);
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/**************************************************************
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* Add the WL decoder module
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* Search the decoder library
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* If we find one, we use the module.
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* Otherwise, we create one and add it to the decoder library
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*/
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DecoderId wl_decoder_id = decoder_lib.find_decoder(wl_addr_size, num_wls,
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true, false, false, readback_port != ModulePortId::INVALID());
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if (DecoderId::INVALID() == wl_decoder_id) {
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wl_decoder_id = decoder_lib.add_decoder(wl_addr_size, num_wls, true, false, false, readback_port != ModulePortId::INVALID());
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}
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VTR_ASSERT(DecoderId::INVALID() != wl_decoder_id);
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/* Create a module if not existed yet */
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std::string wl_decoder_module_name = generate_memory_decoder_subckt_name(wl_addr_size, num_wls);
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ModuleId wl_decoder_module = module_manager.find_module(wl_decoder_module_name);
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if (ModuleId::INVALID() == wl_decoder_module) {
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/* BL decoder has the same ports as the frame-based decoders
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* We reuse it here
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*/
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wl_decoder_module = build_wl_memory_decoder_module(module_manager,
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decoder_lib,
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wl_decoder_id);
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}
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VTR_ASSERT(ModuleId::INVALID() != wl_decoder_module);
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size_t curr_wl_decoder_instance_id = module_manager.num_instance(top_module, wl_decoder_module);
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module_manager.add_child_module(top_module, wl_decoder_module);
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/**************************************************************
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* Add module nets from the top module to BL decoder's inputs
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*/
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ModulePortId bl_decoder_en_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME));
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BasicPort bl_decoder_en_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_en_port);
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ModulePortId bl_decoder_addr_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
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BasicPort bl_decoder_addr_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_addr_port);
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ModulePortId bl_decoder_din_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_IN_PORT_NAME));
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BasicPort bl_decoder_din_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_din_port);
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/* Data in port of the local BL decoder should always be 1 */
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VTR_ASSERT(1 == bl_decoder_din_port_info.get_width());
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/* Top module Enable port -> BL Decoder Enable port */
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add_module_bus_nets(module_manager,
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top_module,
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top_module, 0, en_port,
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bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_en_port);
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/* Top module Address port -> BL Decoder Address port */
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add_module_bus_nets(module_manager,
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top_module,
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top_module, 0, bl_addr_port,
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bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_addr_port);
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/* Top module data_in port -> BL Decoder data_in port:
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* Note that each region has independent data_in connection from the top-level module
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* The pin index is the configuration region index
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*/
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ModuleNetId din_net = create_module_source_pin_net(module_manager, top_module,
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top_module, 0,
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din_port,
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din_port_info.pins()[size_t(config_region)]);
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VTR_ASSERT(ModuleNetId::INVALID() != din_net);
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/* Configure the net sink */
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module_manager.add_module_net_sink(top_module, din_net, bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_din_port, bl_decoder_din_port_info.pins()[0]);
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/**************************************************************
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* Add module nets from the top module to WL decoder's inputs
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*/
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ModulePortId wl_decoder_en_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME));
|
|
|
|
|
BasicPort wl_decoder_en_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_en_port);
|
|
|
|
|
|
|
|
|
|
ModulePortId wl_decoder_addr_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
|
2021-09-20 18:05:36 -05:00
|
|
|
BasicPort wl_decoder_addr_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_addr_port);
|
|
|
|
|
|
|
|
|
|
ModulePortId wl_decoder_readback_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_READBACK_PORT_NAME));
|
|
|
|
|
BasicPort wl_decoder_readback_port_info;
|
|
|
|
|
if (wl_decoder_readback_port) {
|
|
|
|
|
wl_decoder_readback_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_readback_port);
|
|
|
|
|
}
|
2021-09-05 15:23:38 -05:00
|
|
|
|
|
|
|
|
/* Top module Enable port -> WL Decoder Enable port */
|
|
|
|
|
add_module_bus_nets(module_manager,
|
|
|
|
|
top_module,
|
|
|
|
|
top_module, 0, en_port,
|
|
|
|
|
wl_decoder_module, curr_wl_decoder_instance_id, wl_decoder_en_port);
|
|
|
|
|
|
|
|
|
|
/* Top module Address port -> WL Decoder Address port */
|
|
|
|
|
add_module_bus_nets(module_manager,
|
|
|
|
|
top_module,
|
|
|
|
|
top_module, 0, wl_addr_port,
|
|
|
|
|
wl_decoder_module, curr_wl_decoder_instance_id, wl_decoder_addr_port);
|
|
|
|
|
|
2021-09-20 18:05:36 -05:00
|
|
|
/* Top module readback port -> WL Decoder readback port */
|
|
|
|
|
if (wl_decoder_readback_port) {
|
|
|
|
|
add_module_bus_nets(module_manager,
|
|
|
|
|
top_module,
|
|
|
|
|
top_module, 0, readback_port,
|
|
|
|
|
wl_decoder_module, curr_wl_decoder_instance_id, wl_decoder_readback_port);
|
|
|
|
|
}
|
|
|
|
|
|
2021-09-05 15:23:38 -05:00
|
|
|
/**************************************************************
|
2021-09-05 19:49:01 -05:00
|
|
|
* Precompute the BLs and WLs distribution across the FPGA fabric
|
|
|
|
|
* The distribution is a matrix which contains the starting index of BL/WL for each column or row
|
2021-09-05 15:23:38 -05:00
|
|
|
*/
|
2021-09-05 22:45:56 -05:00
|
|
|
std::pair<int, int> child_x_range = compute_memory_bank_regional_configurable_child_x_range(module_manager, top_module, config_region);
|
|
|
|
|
std::pair<int, int> child_y_range = compute_memory_bank_regional_configurable_child_y_range(module_manager, top_module, config_region);
|
2021-09-05 15:23:38 -05:00
|
|
|
|
2021-09-05 22:45:56 -05:00
|
|
|
std::map<int, size_t> num_bls_per_tile = compute_memory_bank_regional_bitline_numbers_per_tile(module_manager, top_module,
|
|
|
|
|
config_region,
|
|
|
|
|
circuit_lib, sram_model);
|
|
|
|
|
std::map<int, size_t> num_wls_per_tile = compute_memory_bank_regional_wordline_numbers_per_tile(module_manager, top_module,
|
|
|
|
|
config_region,
|
2021-09-15 13:27:55 -05:00
|
|
|
circuit_lib, sram_model);
|
2021-09-05 19:49:01 -05:00
|
|
|
|
2021-09-05 22:45:56 -05:00
|
|
|
std::map<int, size_t> bl_start_index_per_tile = compute_memory_bank_regional_blwl_start_index_per_tile(child_x_range, num_bls_per_tile);
|
|
|
|
|
std::map<int, size_t> wl_start_index_per_tile = compute_memory_bank_regional_blwl_start_index_per_tile(child_y_range, num_wls_per_tile);
|
2021-09-05 19:49:01 -05:00
|
|
|
|
|
|
|
|
/**************************************************************
|
|
|
|
|
* Add nets from BL data out to each configurable child
|
|
|
|
|
* BL data output pins are connected to the BL input pins of each PB/CB/SB
|
|
|
|
|
* For all the PB/CB/SB in the same column, they share the same set of BLs
|
|
|
|
|
* A quick example
|
|
|
|
|
*
|
|
|
|
|
* BL[i .. i + sqrt(N)]
|
|
|
|
|
* |
|
|
|
|
|
* | CLB[1][H]
|
|
|
|
|
* | +---------+
|
|
|
|
|
* | | SRAM |
|
|
|
|
|
* +-->| [0..N] |
|
|
|
|
|
* | +---------+
|
|
|
|
|
* |
|
|
|
|
|
* ...
|
|
|
|
|
* | CLB[1][1]
|
|
|
|
|
* | +---------+
|
|
|
|
|
* | | SRAM |
|
|
|
|
|
* +-->| [0..N] |
|
|
|
|
|
* | +---------+
|
|
|
|
|
* |
|
|
|
|
|
*/
|
2021-09-05 15:23:38 -05:00
|
|
|
ModulePortId bl_decoder_dout_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
|
|
|
|
|
BasicPort bl_decoder_dout_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_dout_port);
|
|
|
|
|
|
|
|
|
|
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
|
|
|
|
|
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
|
|
|
|
|
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id];
|
|
|
|
|
|
|
|
|
|
size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id];
|
|
|
|
|
|
|
|
|
|
/* Find the BL port */
|
|
|
|
|
ModulePortId child_bl_port = module_manager.find_module_port(child_module, std::string(MEMORY_BL_PORT_NAME));
|
|
|
|
|
BasicPort child_bl_port_info = module_manager.module_port(child_module, child_bl_port);
|
|
|
|
|
|
2021-09-05 19:49:01 -05:00
|
|
|
size_t cur_bl_index = 0;
|
|
|
|
|
|
2021-09-05 15:23:38 -05:00
|
|
|
for (const size_t& sink_bl_pin : child_bl_port_info.pins()) {
|
2021-09-15 13:27:55 -05:00
|
|
|
size_t bl_pin_id = bl_start_index_per_tile[coord.x()] + cur_bl_index;
|
2021-09-05 15:23:38 -05:00
|
|
|
/* Find the BL decoder data index:
|
2021-09-05 19:49:01 -05:00
|
|
|
* It should be the starting index plus an offset which is the residual when divided by the number of BLs in this tile
|
2021-09-05 15:23:38 -05:00
|
|
|
*/
|
2021-09-10 17:05:46 -05:00
|
|
|
VTR_ASSERT(bl_pin_id < bl_decoder_dout_port_info.pins().size());
|
2021-09-05 15:23:38 -05:00
|
|
|
|
|
|
|
|
/* Create net */
|
|
|
|
|
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
|
|
|
|
|
bl_decoder_module, curr_bl_decoder_instance_id,
|
|
|
|
|
bl_decoder_dout_port,
|
|
|
|
|
bl_decoder_dout_port_info.pins()[bl_pin_id]);
|
|
|
|
|
VTR_ASSERT(ModuleNetId::INVALID() != net);
|
|
|
|
|
|
|
|
|
|
/* Add net sink */
|
|
|
|
|
module_manager.add_module_net_sink(top_module, net,
|
|
|
|
|
child_module, child_instance, child_bl_port, sink_bl_pin);
|
|
|
|
|
|
|
|
|
|
cur_bl_index++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**************************************************************
|
|
|
|
|
* Add nets from WL data out to each configurable child
|
|
|
|
|
*/
|
|
|
|
|
ModulePortId wl_decoder_dout_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
|
|
|
|
|
BasicPort wl_decoder_dout_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_dout_port);
|
|
|
|
|
|
|
|
|
|
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
|
|
|
|
|
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
|
2021-09-05 19:49:01 -05:00
|
|
|
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id];
|
|
|
|
|
|
2021-09-05 15:23:38 -05:00
|
|
|
size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id];
|
|
|
|
|
|
|
|
|
|
/* Find the WL port */
|
|
|
|
|
ModulePortId child_wl_port = module_manager.find_module_port(child_module, std::string(MEMORY_WL_PORT_NAME));
|
|
|
|
|
BasicPort child_wl_port_info = module_manager.module_port(child_module, child_wl_port);
|
|
|
|
|
|
2021-09-05 19:49:01 -05:00
|
|
|
size_t cur_wl_index = 0;
|
|
|
|
|
|
2021-09-05 15:23:38 -05:00
|
|
|
for (const size_t& sink_wl_pin : child_wl_port_info.pins()) {
|
2021-09-15 13:27:55 -05:00
|
|
|
size_t wl_pin_id = wl_start_index_per_tile[coord.y()] + cur_wl_index;
|
2021-09-10 17:05:46 -05:00
|
|
|
VTR_ASSERT(wl_pin_id < wl_decoder_dout_port_info.pins().size());
|
2021-09-05 15:23:38 -05:00
|
|
|
|
|
|
|
|
/* Create net */
|
|
|
|
|
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
|
|
|
|
|
wl_decoder_module, curr_wl_decoder_instance_id,
|
|
|
|
|
wl_decoder_dout_port,
|
|
|
|
|
wl_decoder_dout_port_info.pins()[wl_pin_id]);
|
|
|
|
|
VTR_ASSERT(ModuleNetId::INVALID() != net);
|
|
|
|
|
|
|
|
|
|
/* Add net sink */
|
|
|
|
|
module_manager.add_module_net_sink(top_module, net,
|
|
|
|
|
child_module, child_instance, child_wl_port, sink_wl_pin);
|
2021-09-10 17:05:46 -05:00
|
|
|
|
2021-09-05 15:23:38 -05:00
|
|
|
cur_wl_index++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-09-20 18:05:36 -05:00
|
|
|
/**************************************************************
|
|
|
|
|
* Optional: Add nets from WLR data out to each configurable child
|
|
|
|
|
*/
|
|
|
|
|
ModulePortId wl_decoder_data_ren_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_READ_ENABLE_PORT_NAME));
|
|
|
|
|
BasicPort wl_decoder_data_ren_port_info;
|
|
|
|
|
if (wl_decoder_data_ren_port) {
|
|
|
|
|
wl_decoder_data_ren_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_data_ren_port);
|
|
|
|
|
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
|
|
|
|
|
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
|
|
|
|
|
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id];
|
|
|
|
|
|
|
|
|
|
size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id];
|
|
|
|
|
|
|
|
|
|
/* Find the WL port */
|
|
|
|
|
ModulePortId child_wlr_port = module_manager.find_module_port(child_module, std::string(MEMORY_WLR_PORT_NAME));
|
|
|
|
|
BasicPort child_wlr_port_info = module_manager.module_port(child_module, child_wlr_port);
|
|
|
|
|
|
|
|
|
|
size_t cur_wlr_index = 0;
|
|
|
|
|
|
|
|
|
|
for (const size_t& sink_wlr_pin : child_wlr_port_info.pins()) {
|
|
|
|
|
size_t wlr_pin_id = wl_start_index_per_tile[coord.y()] + cur_wlr_index;
|
|
|
|
|
VTR_ASSERT(wlr_pin_id < wl_decoder_data_ren_port_info.pins().size());
|
|
|
|
|
|
|
|
|
|
/* Create net */
|
|
|
|
|
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
|
|
|
|
|
wl_decoder_module, curr_wl_decoder_instance_id,
|
|
|
|
|
wl_decoder_data_ren_port,
|
|
|
|
|
wl_decoder_data_ren_port_info.pins()[wlr_pin_id]);
|
|
|
|
|
VTR_ASSERT(ModuleNetId::INVALID() != net);
|
|
|
|
|
|
|
|
|
|
/* Add net sink */
|
|
|
|
|
module_manager.add_module_net_sink(top_module, net,
|
|
|
|
|
child_module, child_instance, child_wlr_port, sink_wlr_pin);
|
|
|
|
|
|
|
|
|
|
cur_wlr_index++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-09-05 15:23:38 -05:00
|
|
|
/**************************************************************
|
|
|
|
|
* Add the BL and WL decoders to the end of configurable children list
|
|
|
|
|
* Note: this MUST be done after adding all the module nets to other regular configurable children
|
|
|
|
|
*/
|
|
|
|
|
module_manager.add_configurable_child(top_module, bl_decoder_module, curr_bl_decoder_instance_id);
|
|
|
|
|
module_manager.add_configurable_child_to_region(top_module,
|
|
|
|
|
config_region,
|
|
|
|
|
bl_decoder_module,
|
|
|
|
|
curr_bl_decoder_instance_id,
|
|
|
|
|
module_manager.configurable_children(top_module).size() - 1);
|
|
|
|
|
|
|
|
|
|
module_manager.add_configurable_child(top_module, wl_decoder_module, curr_wl_decoder_instance_id);
|
|
|
|
|
module_manager.add_configurable_child_to_region(top_module,
|
|
|
|
|
config_region,
|
|
|
|
|
wl_decoder_module,
|
|
|
|
|
curr_wl_decoder_instance_id,
|
|
|
|
|
module_manager.configurable_children(top_module).size() - 1);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
} /* end namespace openfpga */
|
