*``<architecture_file>`` is the target :ref:`FPGA architecture <fpga_architecture_description>`
*``<circuit_file>`` The list of files in the benchmark (Supports ../directory/\*.v)
*``<top_module_name>`` The name of the top level module in Verilog project
..note::
The script will create a ``tmp`` run directory in base OpenFPGA path, unless otherwise specified with the :option:`--run_dir` option.
All stages of the flow will be run within run directory.
Several intermediate files will be generated and maintian in run directory.
The path variables declared in architecture XML file will be resolved with absolute path and copied to the ``tmp/arch`` directory before executing flow.
All the benchmark files provided will be copied to ``tmp/bench`` directory without maintaining any directory structure.
**Users should ensure that no important files are kept in this directory as script will clear directory before each execution**
*``<options>`` are additional arguments passed to ``run_fpga_flow.py`` (described below),
*``<vpr_options>`` Any argument prefixed with ``--vpr-*`` will be forwarded to vpr script as it is. The detail of supported vpr argument is available ``Add corrrect reference``
*``<fpga-verilog_options>`` are any arguments not recognized by ``run_vtr_flow.pl``. These will be forwarded to VPR.
*``<ace_options>`` these arguments will be passed to ACE activity estimator program
will run the VTR flow to map the circuit ``my_circuit.v`` onto the architecture ``my_arch.xml``; the arguments ``--pack`` and ``--place`` will be passed to VPR (since they are unrecognized arguments to ``run_vtr_flow.pl``).
They will cause VPR to perform only :ref:`packing and placement <general_options>`.
Detailed Command-line Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
..Note:: All the commnadline arguments starting with ``vpr_*`` , ``fpga-verilog_*`` , ``fpga-spice_*`` or ``fpga-bitstream_*`` will be passed to VPR without suffix
General Arguments
^^^^^^^^^^^^^^^^^
..option:: --top_module <name>
Provide top module name of the benchmark. Default ``top``
This option allows the user to provide a custom Yosys template while running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Alternately, user can create a copy and modify according to their need. Yosys template script supports ``TOP_MODULE````READ_VERILOG_FILE````LUT_SIZE`` & ``OUTPUT_BLIF`` variables. In case if ``--verific`` option is provided then ``ADD_INCLUDE_DIR``, ``ADD_LIBRARY_DIR``, ``ADD_BLACKBOX_MODULES``, ``READ_HDL_FILE`` (should be used instead of ``READ_VERILOG_FILE``) and ``READ_LIBRARY`` additional varialbes are supported. The variables can be used as ``${var_name}``.
This option allows the user to provide an alternate Yosys template to rewrite Verilog netlist while running a yosys_vpr flow. The alternate Yosys template script supports all of the main Yosys template script variables.
..option:: --verific
This option specifies to use Verific as a frontend for Yosys while running a yosys_vpr flow.
The following standards are used by default for reading input HDL files:
* Verilog - ``vlog95``
* System Verilog - ``sv2012``
* VHDL - ``vhdl2008``
The option should be used only with custom Yosys template containing Verific commands.
Performs VPR implementation to get minimum channel width and then perform fixed channel rerouting with ``percentage_slack`` increase in the channel width.
