2020-02-17 18:57:43 -06:00
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/********************************************************************
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* This file includes functions to compress the hierachy of routing architecture
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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#include "vtr_log.h"
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2020-04-08 17:18:05 -05:00
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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2020-02-25 23:39:42 -06:00
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#include "build_physical_truth_table.h"
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2020-02-17 18:57:43 -06:00
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#include "repack.h"
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#include "openfpga_repack.h"
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/* Include global variables of VPR */
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#include "globals.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* A wrapper function to call the fabric_verilog function of FPGA-Verilog
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*******************************************************************/
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2020-04-08 17:18:05 -05:00
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int repack(OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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2020-02-17 18:57:43 -06:00
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CommandOptionId opt_verbose = cmd.option("verbose");
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pack_physical_pbs(g_vpr_ctx.device(),
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2020-02-20 21:26:20 -06:00
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g_vpr_ctx.atom(),
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g_vpr_ctx.clustering(),
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2020-02-20 14:24:34 -06:00
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openfpga_ctx.mutable_vpr_device_annotation(),
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2020-02-17 18:57:43 -06:00
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openfpga_ctx.mutable_vpr_clustering_annotation(),
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cmd_context.option_enable(cmd, opt_verbose));
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2020-02-25 23:39:42 -06:00
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build_physical_lut_truth_tables(openfpga_ctx.mutable_vpr_clustering_annotation(),
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g_vpr_ctx.atom(),
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g_vpr_ctx.clustering(),
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openfpga_ctx.vpr_device_annotation(),
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openfpga_ctx.arch().circuit_lib);
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2020-04-08 17:18:05 -05:00
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/* TODO: should identify the error code from internal function execution */
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return CMD_EXEC_SUCCESS;
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2020-02-17 18:57:43 -06:00
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}
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} /* end namespace openfpga */
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