OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/and4/and4.v

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/////////////////////////////////////////
// Functionality: 4-input AND
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module and4(
a,
b,
c,
d,
e);
input wire a;
input wire b;
input wire c;
input wire d;
output wire e;
assign e = a & b & c & d;
endmodule