23 lines
316 B
Verilog
23 lines
316 B
Verilog
/////////////////////////////////////////
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// Functionality: 4-input AND
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// Author: Xifan Tang
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////////////////////////////////////////
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`timescale 1ns / 1ps
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module and4(
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a,
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b,
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c,
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d,
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e);
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input wire a;
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input wire b;
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input wire c;
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input wire d;
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output wire e;
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assign e = a & b & c & d;
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endmodule
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