OpenFPGA/docs/source/tutorials/design_flow/index.rst

mirror of https://github.com/lnis-uofu/OpenFPGA.git
.. _design_flow_tutorials:
   Design Flows

Design Flows
------------
 
.. toctree::
   :maxdepth: 2

   blif_to_verification

   verilog_to_gds2
re organize tutorials 2020-05-24 19:09:48 -05:00			`.. _design_flow_tutorials:`
			`Design Flows`

			`Design Flows`
			`------------`

			`.. toctree::`
			`:maxdepth: 2`

add tutorial for full testbench run 2020-05-25 01:31:01 -05:00			`blif_to_verification`

renaming design flows in documentation 2020-05-25 00:03:54 -05:00			`verilog_to_gds2`