coriolis/crlcore
Jean-Paul Chaput 909f86b4fc Added support for IEEE VHDL in the Vst parser (std_logic).
* New: In CRL Core, in VstParser, support IEEE VHDL, with tokens
    <library> and <use>. If "use IEEE.std_logic_1164.ALL" is present
    the file will be considered to be IEEE compliant.
      To be precise, the parser now support any mix between Alliance
    and IEEE VHDL. So you can have both <std_logic> and <wor_bit>
    in the same file, but it is unclean to do that.
      The two extensions ".vhd" & ".vhdl" are supported.
      The drivers still always creates Alliance VHDL.
2015-05-10 17:16:00 +02:00
..
cmake_modules New Library Manager Widget. Access with Tools menu or CTRL+M. 2015-05-09 17:03:17 +02:00
doc Happy new year 2015! 2015-03-17 16:56:55 +01:00
etc Add a state to Cell to know if is placed and/or routed. 2015-04-16 16:52:33 +02:00
python Support for Net alias names. Blif parser enhancements. 2015-04-16 15:40:02 +02:00
src Added support for IEEE VHDL in the Vst parser (std_logic). 2015-05-10 17:16:00 +02:00
CMakeLists.txt Python Script launcher extended to accomodate Chams. 2015-03-17 16:31:24 +01:00