Added support for IEEE VHDL in the Vst parser (std_logic).
* New: In CRL Core, in VstParser, support IEEE VHDL, with tokens
<library> and <use>. If "use IEEE.std_logic_1164.ALL" is present
the file will be considered to be IEEE compliant.
To be precise, the parser now support any mix between Alliance
and IEEE VHDL. So you can have both <std_logic> and <wor_bit>
in the same file, but it is unclean to do that.
The two extensions ".vhd" & ".vhdl" are supported.
The drivers still always creates Alliance VHDL.
This commit is contained in:
Jean-Paul Chaput
parent
1b79ef75c9
commit
909f86b4fc
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@ -77,6 +77,14 @@ namespace CRL {
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, "VHDL Structural"
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, CellLoader::Native
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, Catalog::State::Logical ) );
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loaders->addLoader( new CellLoader("vhd"
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, "VHDL Structural (IEEE)"
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, CellLoader::Native
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, Catalog::State::Logical ) );
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loaders->addLoader( new CellLoader("vhdl"
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, "VHDL Structural (IEEE)"
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, CellLoader::Native
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, Catalog::State::Logical ) );
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loaders->addLoader( new CellLoader("ap"
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, "Alliance Physical"
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, CellLoader::Native
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@ -1,66 +1,28 @@
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// -*- C++ -*-
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//
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// This file is part of the Coriolis Project.
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// Copyright (C) Laboratoire LIP6 - Departement ASIM
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// Universite Pierre et Marie Curie
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// This file is part of the Coriolis Software.
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// Copyright (c) UPMC 2008-2015, All Rights Reserved
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//
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// Main contributors :
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// Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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// Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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// Hugo Clément <Hugo.Clement@lip6.fr>
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// Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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// Damien Dupuis <Damien.Dupuis@lip6.fr>
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// Christian Masson <Christian.Masson@lip6.fr>
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// Marek Sroka <Marek.Sroka@lip6.fr>
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//
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// The Coriolis Project is free software; you can redistribute it
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// and/or modify it under the terms of the GNU General Public License
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// as published by the Free Software Foundation; either version 2 of
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// the License, or (at your option) any later version.
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//
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// The Coriolis Project is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the Coriolis Project; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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//
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// License-Tag
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// Authors-Tag
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// ===================================================================
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//
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// $Id$
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//
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// x-----------------------------------------------------------------x
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// | |
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// +-----------------------------------------------------------------+
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// | C O R I O L I S |
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// | Alliance / Hurricane Interface |
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// | |
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// | Author : Jean-Paul CHAPUT |
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// | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
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// | E-mail : Jean-Paul.Chaput@lip6.fr |
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// | =============================================================== |
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// | C++ Module : "./ParserDriver.cpp" |
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// | *************************************************************** |
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// | U p d a t e s |
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// | |
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// x-----------------------------------------------------------------x
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// | C++ Module : "./ParsersDrivers.cpp" |
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// +-----------------------------------------------------------------+
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#include "hurricane/DBo.h"
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#include "crlcore/Utilities.h"
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#include "crlcore/Environment.h"
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#include "crlcore/Catalog.h"
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#include "crlcore/ParsersDrivers.h"
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#include "Ap.h"
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#include "Vst.h"
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#include "Spice.h"
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#include "openaccess/OpenAccess.h"
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#include "hurricane/DBo.h"
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#include "crlcore/Utilities.h"
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#include "crlcore/Environment.h"
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#include "crlcore/Catalog.h"
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#include "crlcore/ParsersDrivers.h"
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#include "Ap.h"
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#include "Vst.h"
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#include "Spice.h"
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#include "openaccess/OpenAccess.h"
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namespace {
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@ -74,18 +36,13 @@ namespace {
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" Attempt to overwrite registered parser for format \"%s\"\n"
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" and extention \"%s\".\n";
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} // End of anonymous namespace.
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} // Anonymous namespace.
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namespace CRL {
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// x-----------------------------------------------------------------x
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// | Variables Definitions |
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// x-----------------------------------------------------------------x
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const char* BadParserType =
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"%s:\n\n"
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" No registered parser avalaible to load cell \"%s\"\n"
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@ -104,9 +61,8 @@ namespace CRL {
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" (neither logical or physical has been set)\n";
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// x-----------------------------------------------------------------x
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// | Methods of Class "ParserFormatSlot" |
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// x-----------------------------------------------------------------x
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// -------------------------------------------------------------------
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// Class : "ParserFormatSlot"
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bool ParserFormatSlot::cend () {
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@ -203,18 +159,19 @@ namespace CRL {
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}
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// x-----------------------------------------------------------------x
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// | Methods of Class "ParsersMap" |
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// x-----------------------------------------------------------------x
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// -------------------------------------------------------------------
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// Class : "ParsersMap"
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ParsersMap::ParsersMap (): map<Name,ParserFormatSlot>()
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{
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// Register the Alliance default parsers.
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registerSlot ( "ap" , (CellParser_t*)apParser , "ap" );
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registerSlot ( "vst" , (CellParser_t*)vstParser , "vst" );
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registerSlot ( "vst" , (CellParser_t*)vstParser , "vbe" );
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registerSlot ( "spi" , (CellParser_t*)spiceParser , "spi" );
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registerSlot ( "ap" , (CellParser_t*)apParser , "ap" );
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registerSlot ( "vst" , (CellParser_t*)vstParser , "vst" );
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registerSlot ( "vst" , (CellParser_t*)vstParser , "vbe" );
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registerSlot ( "vst" , (CellParser_t*)vstParser , "vhd" );
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registerSlot ( "vst" , (CellParser_t*)vstParser , "vhdl" );
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registerSlot ( "spi" , (CellParser_t*)spiceParser , "spi" );
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registerSlot ( "oa" , (CellParser_t*)OpenAccess::oaCellParser , "oa" );
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//registerSlot ( "oa" , (LibraryParser_t*)OpenAccess::oaLibParser, "oa" );
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}
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@ -316,9 +273,8 @@ namespace CRL {
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// x-----------------------------------------------------------------x
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// | Methods of Class "DriversMap" |
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// x-----------------------------------------------------------------x
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// -------------------------------------------------------------------
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// Class : "DriversMap"
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DriversMap::DriversMap () : map<Name,DriverSlot>()
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@ -1,7 +1,7 @@
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%{
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// This file is part of the Coriolis Software.
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// Copyright (c) UPMC 2008-2014, All Rights Reserved
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// Copyright (c) UPMC 2008-2015, All Rights Reserved
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//
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// +-----------------------------------------------------------------+
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// | C O R I O L I S |
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@ -67,6 +67,7 @@ namespace Vst {
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extern void incVhdLineNumber ();
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extern void ClearIdentifiers ();
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void checkForIeee ( bool ieeeEnabled );
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class Constraint {
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@ -137,6 +138,8 @@ namespace Vst {
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bool _masterPort;
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bool _firstPass;
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bool _behavioral;
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bool _ieeeVhdl;
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bool _ieeeWarned;
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public:
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YaccState ( const string& vhdFileName )
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: _vhdFileName (vhdFileName)
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@ -156,6 +159,8 @@ namespace Vst {
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, _masterPort (true)
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, _firstPass (true)
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, _behavioral (false)
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, _ieeeVhdl (false)
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, _ieeeWarned (false)
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{ }
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bool pushCell ( Name );
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};
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@ -314,6 +319,8 @@ namespace Vst {
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%token SEVERITY
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%token SIGNAL
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%token _STABLE
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%token STD_LOGIC
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%token STD_LOGIC_VECTOR
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%token STRING
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%token SUBTYPE
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%token THEN
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@ -366,10 +373,59 @@ namespace Vst {
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%%
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design_file
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: entity_declaration
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: ...libraries_declarations..
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entity_declaration
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architecture_body
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;
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...libraries_declarations..
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: /* Empty */
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| library_or_use_statement
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...libraries_declarations..
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;
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library_or_use_statement
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: library_statement
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| use_statement
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;
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library_statement
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: LIBRARY
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Identifier
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Semicolon_ERR
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;
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use_statement
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: USE
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identifier_path
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Semicolon_ERR
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{ bool ieeeVhdl = (Vst::states->_identifiersList.size() == 3);
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for ( size_t i=0 ; ieeeVhdl and (i<Vst::states->_identifiersList.size()) ; ++i ) {
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switch ( i ) {
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case 0: if (*(Vst::states->_identifiersList[i]) == "ieee") continue;
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case 1: if (*(Vst::states->_identifiersList[i]) == "std_logic_1164") continue;
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case 2: if (*(Vst::states->_identifiersList[i]) == "all") continue;
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}
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ieeeVhdl = false;
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break;
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}
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Vst::states->_ieeeVhdl |= ieeeVhdl;
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Vst::states->_identifiersList.clear();
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}
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;
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identifier_path
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: path_element
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| identifier_path
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Dot
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path_element
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;
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path_element
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: Identifier { Vst::states->_identifiersList.push_back( $1 ); }
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| ALL { Vst::states->_identifiersList.push_back( new string("all") ); }
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;
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entity_declaration
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: ENTITY
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.simple_name.
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@ -1075,19 +1131,21 @@ type_convertion
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;
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type_mark
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: BIT { $$ = Net::Direction::UNDEFINED; }
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| WOR_BIT { $$ = Net::Direction::ConnWiredOr; }
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| MUX_BIT { $$ = Net::Direction::ConnTristate; }
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| BIT_VECTOR { $$ = Net::Direction::UNDEFINED; }
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| WOR_VECTOR { $$ = Net::Direction::ConnWiredOr; }
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| MUX_VECTOR { $$ = Net::Direction::ConnTristate; }
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| INTEGER { $$ = Net::Direction::UNDEFINED; }
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| NATURAL { $$ = Net::Direction::UNDEFINED; }
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| NATURAL_VECTOR { $$ = Net::Direction::UNDEFINED; }
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| POSITIVE { $$ = Net::Direction::UNDEFINED; }
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| STRING { $$ = Net::Direction::UNDEFINED; }
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| _LIST { $$ = Net::Direction::UNDEFINED; }
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| ARG { $$ = Net::Direction::UNDEFINED; }
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: BIT { $$ = Net::Direction::UNDEFINED; }
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| STD_LOGIC { $$ = Net::Direction::UNDEFINED; Vst::checkForIeee(true ); }
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| STD_LOGIC_VECTOR { $$ = Net::Direction::UNDEFINED; Vst::checkForIeee(true ); }
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| WOR_BIT { $$ = Net::Direction::ConnWiredOr; Vst::checkForIeee(false); }
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| MUX_BIT { $$ = Net::Direction::ConnTristate; Vst::checkForIeee(false); }
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| BIT_VECTOR { $$ = Net::Direction::UNDEFINED; Vst::checkForIeee(false); }
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| WOR_VECTOR { $$ = Net::Direction::ConnWiredOr; Vst::checkForIeee(false); }
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| MUX_VECTOR { $$ = Net::Direction::ConnTristate; Vst::checkForIeee(false); }
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| INTEGER { $$ = Net::Direction::UNDEFINED; }
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| NATURAL { $$ = Net::Direction::UNDEFINED; }
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| NATURAL_VECTOR { $$ = Net::Direction::UNDEFINED; }
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| POSITIVE { $$ = Net::Direction::UNDEFINED; }
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| STRING { $$ = Net::Direction::UNDEFINED; }
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| _LIST { $$ = Net::Direction::UNDEFINED; }
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| ARG { $$ = Net::Direction::UNDEFINED; }
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;
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.BUS.
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@ -1185,7 +1243,7 @@ namespace Vst {
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if ( code < 100 )
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cerr << "[ERROR] CParsVst() VHDL Parser, File:<" << states->_vhdFileName
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<< ">, Line:%d" << states->_vhdLineNumber << " Code:" << code << " :\n ";
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<< ">, Line:" << states->_vhdLineNumber << " Code:" << code << " :\n ";
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else {
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if (code < 200)
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cerr << "[ERROR] CParsVst() VHDL Parser, Code:" << code << " :\n ";
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@ -1224,6 +1282,25 @@ namespace Vst {
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}
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// ---------------------------------------------------------------
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// Function : "checkForIeee()".
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void checkForIeee ( bool ieeeEnabled )
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{
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if (not states->_ieeeWarned) {
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if (ieeeEnabled xor states->_ieeeVhdl) {
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states->_ieeeWarned = true;
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ostringstream formatted;
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formatted << "CParsVst() - VHDL Parser, File:<" << Vst::states->_vhdFileName
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<< ">, Line:" << Vst::states->_vhdLineNumber << "\n "
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<< "Mixed IEEE VHDL & Alliance VHDL dialects, you should choose one.";
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cerr << formatted.str() << endl;
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}
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}
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}
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// ---------------------------------------------------------------
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// Function : "getNet()".
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@ -4,7 +4,7 @@
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%{
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// This file is part of the Coriolis Software.
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// Copyright (c) UPMC 2008-2014, All Rights Reserved
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// Copyright (c) UPMC 2008-2015, All Rights Reserved
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//
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// +-----------------------------------------------------------------+
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// | C O R I O L I S |
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@ -53,123 +53,125 @@ namespace {
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VHDLKeywords::VHDLKeywords () {
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(*this)[ "abs" ] = ABS;
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(*this)[ "access" ] = ACCESS;
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(*this)[ "after" ] = AFTER;
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(*this)[ "alias" ] = ALIAS;
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(*this)[ "all" ] = ALL;
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(*this)[ "and" ] = tok_AND;
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(*this)[ "architecture" ] = ARCHITECTURE;
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(*this)[ "arg" ] = ARG;
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(*this)[ "array" ] = ARRAY;
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(*this)[ "assert" ] = ASSERT;
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(*this)[ "attribute" ] = ATTRIBUTE;
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(*this)[ "begin" ] = _BEGIN;
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(*this)[ "bit" ] = BIT;
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(*this)[ "bit_vector" ] = BIT_VECTOR;
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(*this)[ "block" ] = BLOCK;
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(*this)[ "body" ] = BODY;
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(*this)[ "buffer" ] = BUFFER;
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(*this)[ "bus" ] = BUS;
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(*this)[ "case" ] = CASE;
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(*this)[ "component" ] = COMPONENT;
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(*this)[ "configuration" ] = CONFIGURATION;
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(*this)[ "constant" ] = CONSTANT;
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(*this)[ "disconnect" ] = DISCONNECT;
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(*this)[ "downto" ] = DOWNTO;
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(*this)[ "else" ] = ELSE;
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(*this)[ "elsif" ] = ELSIF;
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(*this)[ "end" ] = _END;
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(*this)[ "entity" ] = ENTITY;
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(*this)[ "error" ] = ERROR;
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(*this)[ "exit" ] = _EXIT;
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(*this)[ "file" ] = _FILE;
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(*this)[ "for" ] = FOR;
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(*this)[ "function" ] = FUNCTION;
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(*this)[ "generate" ] = GENERATE;
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(*this)[ "generic" ] = GENERIC;
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(*this)[ "guarded" ] = GUARDED;
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(*this)[ "if" ] = IF;
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(*this)[ "in" ] = _IN;
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(*this)[ "inout" ] = _INOUT;
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(*this)[ "integer" ] = INTEGER;
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(*this)[ "is" ] = IS;
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(*this)[ "label" ] = _LABEL;
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(*this)[ "library" ] = LIBRARY;
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(*this)[ "linkage" ] = _LINKAGE;
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(*this)[ "list" ] = _LIST;
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(*this)[ "loop" ] = LOOP;
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(*this)[ "map" ] = MAP;
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(*this)[ "mod" ] = MOD;
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(*this)[ "mux_bit" ] = MUX_BIT;
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(*this)[ "mux_vector" ] = MUX_VECTOR;
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(*this)[ "nand" ] = _NAND;
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(*this)[ "natural" ] = NATURAL;
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(*this)[ "new" ] = NEW;
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(*this)[ "next" ] = _NEXT;
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(*this)[ "nor" ] = _NOR;
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(*this)[ "not" ] = _NOT;
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(*this)[ "null" ] = tok_NULL;
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(*this)[ "of" ] = OF;
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(*this)[ "on" ] = ON;
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(*this)[ "open" ] = OPEN;
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(*this)[ "or" ] = _OR;
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(*this)[ "others" ] = OTHERS;
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(*this)[ "out" ] = _OUT;
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(*this)[ "package" ] = _PACKAGE;
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(*this)[ "port" ] = PORT;
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(*this)[ "positive" ] = POSITIVE;
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(*this)[ "procedure" ] = PROCEDURE;
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(*this)[ "process" ] = PROCESS;
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(*this)[ "range" ] = RANGE;
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(*this)[ "record" ] = RECORD;
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(*this)[ "reg_bit" ] = REG_BIT;
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(*this)[ "reg_vector" ] = REG_VECTOR;
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(*this)[ "register" ] = REGISTER;
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(*this)[ "rem" ] = REM;
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(*this)[ "report" ] = REPORT;
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(*this)[ "return" ] = RETURN;
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(*this)[ "select" ] = SELECT;
|
||||
(*this)[ "severity" ] = SEVERITY;
|
||||
(*this)[ "signal" ] = SIGNAL;
|
||||
(*this)[ "stable" ] = _STABLE;
|
||||
(*this)[ "string" ] = STRING;
|
||||
(*this)[ "subtype" ] = SUBTYPE;
|
||||
|
||||
(*this)[ "then" ] = THEN;
|
||||
(*this)[ "to" ] = TO;
|
||||
(*this)[ "transport" ] = TRANSPORT;
|
||||
(*this)[ "type" ] = _TYPE;
|
||||
|
||||
(*this)[ "units" ] = UNITS;
|
||||
(*this)[ "until" ] = UNTIL;
|
||||
(*this)[ "use" ] = USE;
|
||||
|
||||
(*this)[ "variable" ] = VARIABLE;
|
||||
|
||||
(*this)[ "wait" ] = WAIT;
|
||||
(*this)[ "warning" ] = WARNING;
|
||||
(*this)[ "when" ] = WHEN;
|
||||
(*this)[ "while" ] = WHILE;
|
||||
(*this)[ "with" ] = WITH;
|
||||
(*this)[ "wor_bit" ] = WOR_BIT;
|
||||
(*this)[ "wor_vector" ] = WOR_VECTOR;
|
||||
|
||||
(*this)[ "xor" ] = _XOR;
|
||||
(*this)[ "abs" ] = ABS;
|
||||
(*this)[ "access" ] = ACCESS;
|
||||
(*this)[ "after" ] = AFTER;
|
||||
(*this)[ "alias" ] = ALIAS;
|
||||
(*this)[ "all" ] = ALL;
|
||||
(*this)[ "and" ] = tok_AND;
|
||||
(*this)[ "architecture" ] = ARCHITECTURE;
|
||||
(*this)[ "arg" ] = ARG;
|
||||
(*this)[ "array" ] = ARRAY;
|
||||
(*this)[ "assert" ] = ASSERT;
|
||||
(*this)[ "attribute" ] = ATTRIBUTE;
|
||||
|
||||
(*this)[ "begin" ] = _BEGIN;
|
||||
(*this)[ "bit" ] = BIT;
|
||||
(*this)[ "bit_vector" ] = BIT_VECTOR;
|
||||
(*this)[ "block" ] = BLOCK;
|
||||
(*this)[ "body" ] = BODY;
|
||||
(*this)[ "buffer" ] = BUFFER;
|
||||
(*this)[ "bus" ] = BUS;
|
||||
|
||||
(*this)[ "case" ] = CASE;
|
||||
(*this)[ "component" ] = COMPONENT;
|
||||
(*this)[ "configuration" ] = CONFIGURATION;
|
||||
(*this)[ "constant" ] = CONSTANT;
|
||||
|
||||
(*this)[ "disconnect" ] = DISCONNECT;
|
||||
(*this)[ "downto" ] = DOWNTO;
|
||||
|
||||
(*this)[ "else" ] = ELSE;
|
||||
(*this)[ "elsif" ] = ELSIF;
|
||||
(*this)[ "end" ] = _END;
|
||||
(*this)[ "entity" ] = ENTITY;
|
||||
(*this)[ "error" ] = ERROR;
|
||||
(*this)[ "exit" ] = _EXIT;
|
||||
|
||||
(*this)[ "file" ] = _FILE;
|
||||
(*this)[ "for" ] = FOR;
|
||||
(*this)[ "function" ] = FUNCTION;
|
||||
|
||||
(*this)[ "generate" ] = GENERATE;
|
||||
(*this)[ "generic" ] = GENERIC;
|
||||
(*this)[ "guarded" ] = GUARDED;
|
||||
|
||||
(*this)[ "if" ] = IF;
|
||||
(*this)[ "in" ] = _IN;
|
||||
(*this)[ "inout" ] = _INOUT;
|
||||
(*this)[ "integer" ] = INTEGER;
|
||||
(*this)[ "is" ] = IS;
|
||||
|
||||
(*this)[ "label" ] = _LABEL;
|
||||
(*this)[ "library" ] = LIBRARY;
|
||||
(*this)[ "linkage" ] = _LINKAGE;
|
||||
(*this)[ "list" ] = _LIST;
|
||||
(*this)[ "loop" ] = LOOP;
|
||||
|
||||
(*this)[ "map" ] = MAP;
|
||||
(*this)[ "mod" ] = MOD;
|
||||
(*this)[ "mux_bit" ] = MUX_BIT;
|
||||
(*this)[ "mux_vector" ] = MUX_VECTOR;
|
||||
|
||||
(*this)[ "nand" ] = _NAND;
|
||||
(*this)[ "natural" ] = NATURAL;
|
||||
(*this)[ "new" ] = NEW;
|
||||
(*this)[ "next" ] = _NEXT;
|
||||
(*this)[ "nor" ] = _NOR;
|
||||
(*this)[ "not" ] = _NOT;
|
||||
(*this)[ "null" ] = tok_NULL;
|
||||
|
||||
(*this)[ "of" ] = OF;
|
||||
(*this)[ "on" ] = ON;
|
||||
(*this)[ "open" ] = OPEN;
|
||||
(*this)[ "or" ] = _OR;
|
||||
(*this)[ "others" ] = OTHERS;
|
||||
(*this)[ "out" ] = _OUT;
|
||||
|
||||
(*this)[ "package" ] = _PACKAGE;
|
||||
(*this)[ "port" ] = PORT;
|
||||
(*this)[ "positive" ] = POSITIVE;
|
||||
(*this)[ "procedure" ] = PROCEDURE;
|
||||
(*this)[ "process" ] = PROCESS;
|
||||
|
||||
(*this)[ "range" ] = RANGE;
|
||||
(*this)[ "record" ] = RECORD;
|
||||
(*this)[ "reg_bit" ] = REG_BIT;
|
||||
(*this)[ "reg_vector" ] = REG_VECTOR;
|
||||
(*this)[ "register" ] = REGISTER;
|
||||
(*this)[ "rem" ] = REM;
|
||||
(*this)[ "report" ] = REPORT;
|
||||
(*this)[ "return" ] = RETURN;
|
||||
|
||||
(*this)[ "select" ] = SELECT;
|
||||
(*this)[ "severity" ] = SEVERITY;
|
||||
(*this)[ "signal" ] = SIGNAL;
|
||||
(*this)[ "stable" ] = _STABLE;
|
||||
(*this)[ "std_logic" ] = STD_LOGIC;
|
||||
(*this)[ "std_logic_vector" ] = STD_LOGIC_VECTOR;
|
||||
(*this)[ "string" ] = STRING;
|
||||
(*this)[ "subtype" ] = SUBTYPE;
|
||||
|
||||
(*this)[ "then" ] = THEN;
|
||||
(*this)[ "to" ] = TO;
|
||||
(*this)[ "transport" ] = TRANSPORT;
|
||||
(*this)[ "type" ] = _TYPE;
|
||||
|
||||
(*this)[ "units" ] = UNITS;
|
||||
(*this)[ "until" ] = UNTIL;
|
||||
(*this)[ "use" ] = USE;
|
||||
|
||||
(*this)[ "variable" ] = VARIABLE;
|
||||
|
||||
(*this)[ "wait" ] = WAIT;
|
||||
(*this)[ "warning" ] = WARNING;
|
||||
(*this)[ "when" ] = WHEN;
|
||||
(*this)[ "while" ] = WHILE;
|
||||
(*this)[ "with" ] = WITH;
|
||||
(*this)[ "wor_bit" ] = WOR_BIT;
|
||||
(*this)[ "wor_vector" ] = WOR_VECTOR;
|
||||
|
||||
(*this)[ "xor" ] = _XOR;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue