From 909f86b4fce4851fc8d99163eb5694bd933be059 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Sun, 10 May 2015 17:16:00 +0200 Subject: [PATCH] Added support for IEEE VHDL in the Vst parser (std_logic). * New: In CRL Core, in VstParser, support IEEE VHDL, with tokens and . If "use IEEE.std_logic_1164.ALL" is present the file will be considered to be IEEE compliant. To be precise, the parser now support any mix between Alliance and IEEE VHDL. So you can have both and in the same file, but it is unclean to do that. The two extensions ".vhd" & ".vhdl" are supported. The drivers still always creates Alliance VHDL. --- crlcore/src/LibraryManager/CellsModel.cpp | 8 + crlcore/src/ccore/ParsersDrivers.cpp | 100 +++----- .../ccore/alliance/vst/VstParserGrammar.yy | 109 ++++++-- .../ccore/alliance/vst/VstParserScanner.ll | 238 +++++++++--------- 4 files changed, 249 insertions(+), 206 deletions(-) diff --git a/crlcore/src/LibraryManager/CellsModel.cpp b/crlcore/src/LibraryManager/CellsModel.cpp index dfcd4e92..12410cb4 100644 --- a/crlcore/src/LibraryManager/CellsModel.cpp +++ b/crlcore/src/LibraryManager/CellsModel.cpp @@ -77,6 +77,14 @@ namespace CRL { , "VHDL Structural" , CellLoader::Native , Catalog::State::Logical ) ); + loaders->addLoader( new CellLoader("vhd" + , "VHDL Structural (IEEE)" + , CellLoader::Native + , Catalog::State::Logical ) ); + loaders->addLoader( new CellLoader("vhdl" + , "VHDL Structural (IEEE)" + , CellLoader::Native + , Catalog::State::Logical ) ); loaders->addLoader( new CellLoader("ap" , "Alliance Physical" , CellLoader::Native diff --git a/crlcore/src/ccore/ParsersDrivers.cpp b/crlcore/src/ccore/ParsersDrivers.cpp index 2ebe9dba..4e18abf1 100644 --- a/crlcore/src/ccore/ParsersDrivers.cpp +++ b/crlcore/src/ccore/ParsersDrivers.cpp @@ -1,66 +1,28 @@ - // -*- C++ -*- // -// This file is part of the Coriolis Project. -// Copyright (C) Laboratoire LIP6 - Departement ASIM -// Universite Pierre et Marie Curie +// This file is part of the Coriolis Software. +// Copyright (c) UPMC 2008-2015, All Rights Reserved // -// Main contributors : -// Christophe Alexandre -// Sophie Belloeil -// Hugo Clément -// Jean-Paul Chaput -// Damien Dupuis -// Christian Masson -// Marek Sroka -// -// The Coriolis Project is free software; you can redistribute it -// and/or modify it under the terms of the GNU General Public License -// as published by the Free Software Foundation; either version 2 of -// the License, or (at your option) any later version. -// -// The Coriolis Project is distributed in the hope that it will be -// useful, but WITHOUT ANY WARRANTY; without even the implied warranty -// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with the Coriolis Project; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 -// USA -// -// License-Tag -// Authors-Tag -// =================================================================== -// -// $Id$ -// -// x-----------------------------------------------------------------x -// | | +// +-----------------------------------------------------------------+ // | C O R I O L I S | // | Alliance / Hurricane Interface | // | | // | Author : Jean-Paul CHAPUT | -// | E-mail : Jean-Paul.Chaput@asim.lip6.fr | +// | E-mail : Jean-Paul.Chaput@lip6.fr | // | =============================================================== | -// | C++ Module : "./ParserDriver.cpp" | -// | *************************************************************** | -// | U p d a t e s | -// | | -// x-----------------------------------------------------------------x +// | C++ Module : "./ParsersDrivers.cpp" | +// +-----------------------------------------------------------------+ - -#include "hurricane/DBo.h" - -#include "crlcore/Utilities.h" -#include "crlcore/Environment.h" -#include "crlcore/Catalog.h" -#include "crlcore/ParsersDrivers.h" -#include "Ap.h" -#include "Vst.h" -#include "Spice.h" -#include "openaccess/OpenAccess.h" +#include "hurricane/DBo.h" +#include "crlcore/Utilities.h" +#include "crlcore/Environment.h" +#include "crlcore/Catalog.h" +#include "crlcore/ParsersDrivers.h" +#include "Ap.h" +#include "Vst.h" +#include "Spice.h" +#include "openaccess/OpenAccess.h" namespace { @@ -74,18 +36,13 @@ namespace { " Attempt to overwrite registered parser for format \"%s\"\n" " and extention \"%s\".\n"; -} // End of anonymous namespace. - +} // Anonymous namespace. namespace CRL { -// x-----------------------------------------------------------------x -// | Variables Definitions | -// x-----------------------------------------------------------------x - const char* BadParserType = "%s:\n\n" " No registered parser avalaible to load cell \"%s\"\n" @@ -104,9 +61,8 @@ namespace CRL { " (neither logical or physical has been set)\n"; -// x-----------------------------------------------------------------x -// | Methods of Class "ParserFormatSlot" | -// x-----------------------------------------------------------------x +// ------------------------------------------------------------------- +// Class : "ParserFormatSlot" bool ParserFormatSlot::cend () { @@ -203,18 +159,19 @@ namespace CRL { } -// x-----------------------------------------------------------------x -// | Methods of Class "ParsersMap" | -// x-----------------------------------------------------------------x +// ------------------------------------------------------------------- +// Class : "ParsersMap" ParsersMap::ParsersMap (): map() { // Register the Alliance default parsers. - registerSlot ( "ap" , (CellParser_t*)apParser , "ap" ); - registerSlot ( "vst" , (CellParser_t*)vstParser , "vst" ); - registerSlot ( "vst" , (CellParser_t*)vstParser , "vbe" ); - registerSlot ( "spi" , (CellParser_t*)spiceParser , "spi" ); + registerSlot ( "ap" , (CellParser_t*)apParser , "ap" ); + registerSlot ( "vst" , (CellParser_t*)vstParser , "vst" ); + registerSlot ( "vst" , (CellParser_t*)vstParser , "vbe" ); + registerSlot ( "vst" , (CellParser_t*)vstParser , "vhd" ); + registerSlot ( "vst" , (CellParser_t*)vstParser , "vhdl" ); + registerSlot ( "spi" , (CellParser_t*)spiceParser , "spi" ); registerSlot ( "oa" , (CellParser_t*)OpenAccess::oaCellParser , "oa" ); //registerSlot ( "oa" , (LibraryParser_t*)OpenAccess::oaLibParser, "oa" ); } @@ -316,9 +273,8 @@ namespace CRL { -// x-----------------------------------------------------------------x -// | Methods of Class "DriversMap" | -// x-----------------------------------------------------------------x +// ------------------------------------------------------------------- +// Class : "DriversMap" DriversMap::DriversMap () : map() diff --git a/crlcore/src/ccore/alliance/vst/VstParserGrammar.yy b/crlcore/src/ccore/alliance/vst/VstParserGrammar.yy index b5bcd60d..340795f1 100644 --- a/crlcore/src/ccore/alliance/vst/VstParserGrammar.yy +++ b/crlcore/src/ccore/alliance/vst/VstParserGrammar.yy @@ -1,7 +1,7 @@ %{ // This file is part of the Coriolis Software. -// Copyright (c) UPMC 2008-2014, All Rights Reserved +// Copyright (c) UPMC 2008-2015, All Rights Reserved // // +-----------------------------------------------------------------+ // | C O R I O L I S | @@ -67,6 +67,7 @@ namespace Vst { extern void incVhdLineNumber (); extern void ClearIdentifiers (); + void checkForIeee ( bool ieeeEnabled ); class Constraint { @@ -137,6 +138,8 @@ namespace Vst { bool _masterPort; bool _firstPass; bool _behavioral; + bool _ieeeVhdl; + bool _ieeeWarned; public: YaccState ( const string& vhdFileName ) : _vhdFileName (vhdFileName) @@ -156,6 +159,8 @@ namespace Vst { , _masterPort (true) , _firstPass (true) , _behavioral (false) + , _ieeeVhdl (false) + , _ieeeWarned (false) { } bool pushCell ( Name ); }; @@ -314,6 +319,8 @@ namespace Vst { %token SEVERITY %token SIGNAL %token _STABLE +%token STD_LOGIC +%token STD_LOGIC_VECTOR %token STRING %token SUBTYPE %token THEN @@ -366,10 +373,59 @@ namespace Vst { %% design_file - : entity_declaration + : ...libraries_declarations.. + entity_declaration architecture_body ; +...libraries_declarations.. + : /* Empty */ + | library_or_use_statement + ...libraries_declarations.. + ; + +library_or_use_statement + : library_statement + | use_statement + ; + +library_statement + : LIBRARY + Identifier + Semicolon_ERR + ; + +use_statement + : USE + identifier_path + Semicolon_ERR + { bool ieeeVhdl = (Vst::states->_identifiersList.size() == 3); + for ( size_t i=0 ; ieeeVhdl and (i_identifiersList.size()) ; ++i ) { + switch ( i ) { + case 0: if (*(Vst::states->_identifiersList[i]) == "ieee") continue; + case 1: if (*(Vst::states->_identifiersList[i]) == "std_logic_1164") continue; + case 2: if (*(Vst::states->_identifiersList[i]) == "all") continue; + } + ieeeVhdl = false; + break; + } + Vst::states->_ieeeVhdl |= ieeeVhdl; + Vst::states->_identifiersList.clear(); + } + ; + +identifier_path + : path_element + | identifier_path + Dot + path_element + ; + +path_element + : Identifier { Vst::states->_identifiersList.push_back( $1 ); } + | ALL { Vst::states->_identifiersList.push_back( new string("all") ); } + ; + entity_declaration : ENTITY .simple_name. @@ -1075,19 +1131,21 @@ type_convertion ; type_mark - : BIT { $$ = Net::Direction::UNDEFINED; } - | WOR_BIT { $$ = Net::Direction::ConnWiredOr; } - | MUX_BIT { $$ = Net::Direction::ConnTristate; } - | BIT_VECTOR { $$ = Net::Direction::UNDEFINED; } - | WOR_VECTOR { $$ = Net::Direction::ConnWiredOr; } - | MUX_VECTOR { $$ = Net::Direction::ConnTristate; } - | INTEGER { $$ = Net::Direction::UNDEFINED; } - | NATURAL { $$ = Net::Direction::UNDEFINED; } - | NATURAL_VECTOR { $$ = Net::Direction::UNDEFINED; } - | POSITIVE { $$ = Net::Direction::UNDEFINED; } - | STRING { $$ = Net::Direction::UNDEFINED; } - | _LIST { $$ = Net::Direction::UNDEFINED; } - | ARG { $$ = Net::Direction::UNDEFINED; } + : BIT { $$ = Net::Direction::UNDEFINED; } + | STD_LOGIC { $$ = Net::Direction::UNDEFINED; Vst::checkForIeee(true ); } + | STD_LOGIC_VECTOR { $$ = Net::Direction::UNDEFINED; Vst::checkForIeee(true ); } + | WOR_BIT { $$ = Net::Direction::ConnWiredOr; Vst::checkForIeee(false); } + | MUX_BIT { $$ = Net::Direction::ConnTristate; Vst::checkForIeee(false); } + | BIT_VECTOR { $$ = Net::Direction::UNDEFINED; Vst::checkForIeee(false); } + | WOR_VECTOR { $$ = Net::Direction::ConnWiredOr; Vst::checkForIeee(false); } + | MUX_VECTOR { $$ = Net::Direction::ConnTristate; Vst::checkForIeee(false); } + | INTEGER { $$ = Net::Direction::UNDEFINED; } + | NATURAL { $$ = Net::Direction::UNDEFINED; } + | NATURAL_VECTOR { $$ = Net::Direction::UNDEFINED; } + | POSITIVE { $$ = Net::Direction::UNDEFINED; } + | STRING { $$ = Net::Direction::UNDEFINED; } + | _LIST { $$ = Net::Direction::UNDEFINED; } + | ARG { $$ = Net::Direction::UNDEFINED; } ; .BUS. @@ -1185,7 +1243,7 @@ namespace Vst { if ( code < 100 ) cerr << "[ERROR] CParsVst() VHDL Parser, File:<" << states->_vhdFileName - << ">, Line:%d" << states->_vhdLineNumber << " Code:" << code << " :\n "; + << ">, Line:" << states->_vhdLineNumber << " Code:" << code << " :\n "; else { if (code < 200) cerr << "[ERROR] CParsVst() VHDL Parser, Code:" << code << " :\n "; @@ -1224,6 +1282,25 @@ namespace Vst { } + // --------------------------------------------------------------- + // Function : "checkForIeee()". + + void checkForIeee ( bool ieeeEnabled ) + { + if (not states->_ieeeWarned) { + if (ieeeEnabled xor states->_ieeeVhdl) { + states->_ieeeWarned = true; + + ostringstream formatted; + formatted << "CParsVst() - VHDL Parser, File:<" << Vst::states->_vhdFileName + << ">, Line:" << Vst::states->_vhdLineNumber << "\n " + << "Mixed IEEE VHDL & Alliance VHDL dialects, you should choose one."; + cerr << formatted.str() << endl; + } + } + } + + // --------------------------------------------------------------- // Function : "getNet()". diff --git a/crlcore/src/ccore/alliance/vst/VstParserScanner.ll b/crlcore/src/ccore/alliance/vst/VstParserScanner.ll index 0f53a3a2..8e751efc 100644 --- a/crlcore/src/ccore/alliance/vst/VstParserScanner.ll +++ b/crlcore/src/ccore/alliance/vst/VstParserScanner.ll @@ -4,7 +4,7 @@ %{ // This file is part of the Coriolis Software. -// Copyright (c) UPMC 2008-2014, All Rights Reserved +// Copyright (c) UPMC 2008-2015, All Rights Reserved // // +-----------------------------------------------------------------+ // | C O R I O L I S | @@ -53,123 +53,125 @@ namespace { VHDLKeywords::VHDLKeywords () { - (*this)[ "abs" ] = ABS; - (*this)[ "access" ] = ACCESS; - (*this)[ "after" ] = AFTER; - (*this)[ "alias" ] = ALIAS; - (*this)[ "all" ] = ALL; - (*this)[ "and" ] = tok_AND; - (*this)[ "architecture" ] = ARCHITECTURE; - (*this)[ "arg" ] = ARG; - (*this)[ "array" ] = ARRAY; - (*this)[ "assert" ] = ASSERT; - (*this)[ "attribute" ] = ATTRIBUTE; - - (*this)[ "begin" ] = _BEGIN; - (*this)[ "bit" ] = BIT; - (*this)[ "bit_vector" ] = BIT_VECTOR; - (*this)[ "block" ] = BLOCK; - (*this)[ "body" ] = BODY; - (*this)[ "buffer" ] = BUFFER; - (*this)[ "bus" ] = BUS; - - (*this)[ "case" ] = CASE; - (*this)[ "component" ] = COMPONENT; - (*this)[ "configuration" ] = CONFIGURATION; - (*this)[ "constant" ] = CONSTANT; - - (*this)[ "disconnect" ] = DISCONNECT; - (*this)[ "downto" ] = DOWNTO; - - (*this)[ "else" ] = ELSE; - (*this)[ "elsif" ] = ELSIF; - (*this)[ "end" ] = _END; - (*this)[ "entity" ] = ENTITY; - (*this)[ "error" ] = ERROR; - (*this)[ "exit" ] = _EXIT; - - (*this)[ "file" ] = _FILE; - (*this)[ "for" ] = FOR; - (*this)[ "function" ] = FUNCTION; - - (*this)[ "generate" ] = GENERATE; - (*this)[ "generic" ] = GENERIC; - (*this)[ "guarded" ] = GUARDED; - - (*this)[ "if" ] = IF; - (*this)[ "in" ] = _IN; - (*this)[ "inout" ] = _INOUT; - (*this)[ "integer" ] = INTEGER; - (*this)[ "is" ] = IS; - - (*this)[ "label" ] = _LABEL; - (*this)[ "library" ] = LIBRARY; - (*this)[ "linkage" ] = _LINKAGE; - (*this)[ "list" ] = _LIST; - (*this)[ "loop" ] = LOOP; - - (*this)[ "map" ] = MAP; - (*this)[ "mod" ] = MOD; - (*this)[ "mux_bit" ] = MUX_BIT; - (*this)[ "mux_vector" ] = MUX_VECTOR; - - (*this)[ "nand" ] = _NAND; - (*this)[ "natural" ] = NATURAL; - (*this)[ "new" ] = NEW; - (*this)[ "next" ] = _NEXT; - (*this)[ "nor" ] = _NOR; - (*this)[ "not" ] = _NOT; - (*this)[ "null" ] = tok_NULL; - - (*this)[ "of" ] = OF; - (*this)[ "on" ] = ON; - (*this)[ "open" ] = OPEN; - (*this)[ "or" ] = _OR; - (*this)[ "others" ] = OTHERS; - (*this)[ "out" ] = _OUT; - - (*this)[ "package" ] = _PACKAGE; - (*this)[ "port" ] = PORT; - (*this)[ "positive" ] = POSITIVE; - (*this)[ "procedure" ] = PROCEDURE; - (*this)[ "process" ] = PROCESS; - - (*this)[ "range" ] = RANGE; - (*this)[ "record" ] = RECORD; - (*this)[ "reg_bit" ] = REG_BIT; - (*this)[ "reg_vector" ] = REG_VECTOR; - (*this)[ "register" ] = REGISTER; - (*this)[ "rem" ] = REM; - (*this)[ "report" ] = REPORT; - (*this)[ "return" ] = RETURN; - - (*this)[ "select" ] = SELECT; - (*this)[ "severity" ] = SEVERITY; - (*this)[ "signal" ] = SIGNAL; - (*this)[ "stable" ] = _STABLE; - (*this)[ "string" ] = STRING; - (*this)[ "subtype" ] = SUBTYPE; - - (*this)[ "then" ] = THEN; - (*this)[ "to" ] = TO; - (*this)[ "transport" ] = TRANSPORT; - (*this)[ "type" ] = _TYPE; - - (*this)[ "units" ] = UNITS; - (*this)[ "until" ] = UNTIL; - (*this)[ "use" ] = USE; - - (*this)[ "variable" ] = VARIABLE; - - (*this)[ "wait" ] = WAIT; - (*this)[ "warning" ] = WARNING; - (*this)[ "when" ] = WHEN; - (*this)[ "while" ] = WHILE; - (*this)[ "with" ] = WITH; - (*this)[ "wor_bit" ] = WOR_BIT; - (*this)[ "wor_vector" ] = WOR_VECTOR; - - (*this)[ "xor" ] = _XOR; + (*this)[ "abs" ] = ABS; + (*this)[ "access" ] = ACCESS; + (*this)[ "after" ] = AFTER; + (*this)[ "alias" ] = ALIAS; + (*this)[ "all" ] = ALL; + (*this)[ "and" ] = tok_AND; + (*this)[ "architecture" ] = ARCHITECTURE; + (*this)[ "arg" ] = ARG; + (*this)[ "array" ] = ARRAY; + (*this)[ "assert" ] = ASSERT; + (*this)[ "attribute" ] = ATTRIBUTE; + + (*this)[ "begin" ] = _BEGIN; + (*this)[ "bit" ] = BIT; + (*this)[ "bit_vector" ] = BIT_VECTOR; + (*this)[ "block" ] = BLOCK; + (*this)[ "body" ] = BODY; + (*this)[ "buffer" ] = BUFFER; + (*this)[ "bus" ] = BUS; + + (*this)[ "case" ] = CASE; + (*this)[ "component" ] = COMPONENT; + (*this)[ "configuration" ] = CONFIGURATION; + (*this)[ "constant" ] = CONSTANT; + + (*this)[ "disconnect" ] = DISCONNECT; + (*this)[ "downto" ] = DOWNTO; + + (*this)[ "else" ] = ELSE; + (*this)[ "elsif" ] = ELSIF; + (*this)[ "end" ] = _END; + (*this)[ "entity" ] = ENTITY; + (*this)[ "error" ] = ERROR; + (*this)[ "exit" ] = _EXIT; + + (*this)[ "file" ] = _FILE; + (*this)[ "for" ] = FOR; + (*this)[ "function" ] = FUNCTION; + + (*this)[ "generate" ] = GENERATE; + (*this)[ "generic" ] = GENERIC; + (*this)[ "guarded" ] = GUARDED; + + (*this)[ "if" ] = IF; + (*this)[ "in" ] = _IN; + (*this)[ "inout" ] = _INOUT; + (*this)[ "integer" ] = INTEGER; + (*this)[ "is" ] = IS; + + (*this)[ "label" ] = _LABEL; + (*this)[ "library" ] = LIBRARY; + (*this)[ "linkage" ] = _LINKAGE; + (*this)[ "list" ] = _LIST; + (*this)[ "loop" ] = LOOP; + + (*this)[ "map" ] = MAP; + (*this)[ "mod" ] = MOD; + (*this)[ "mux_bit" ] = MUX_BIT; + (*this)[ "mux_vector" ] = MUX_VECTOR; + + (*this)[ "nand" ] = _NAND; + (*this)[ "natural" ] = NATURAL; + (*this)[ "new" ] = NEW; + (*this)[ "next" ] = _NEXT; + (*this)[ "nor" ] = _NOR; + (*this)[ "not" ] = _NOT; + (*this)[ "null" ] = tok_NULL; + + (*this)[ "of" ] = OF; + (*this)[ "on" ] = ON; + (*this)[ "open" ] = OPEN; + (*this)[ "or" ] = _OR; + (*this)[ "others" ] = OTHERS; + (*this)[ "out" ] = _OUT; + + (*this)[ "package" ] = _PACKAGE; + (*this)[ "port" ] = PORT; + (*this)[ "positive" ] = POSITIVE; + (*this)[ "procedure" ] = PROCEDURE; + (*this)[ "process" ] = PROCESS; + + (*this)[ "range" ] = RANGE; + (*this)[ "record" ] = RECORD; + (*this)[ "reg_bit" ] = REG_BIT; + (*this)[ "reg_vector" ] = REG_VECTOR; + (*this)[ "register" ] = REGISTER; + (*this)[ "rem" ] = REM; + (*this)[ "report" ] = REPORT; + (*this)[ "return" ] = RETURN; + + (*this)[ "select" ] = SELECT; + (*this)[ "severity" ] = SEVERITY; + (*this)[ "signal" ] = SIGNAL; + (*this)[ "stable" ] = _STABLE; + (*this)[ "std_logic" ] = STD_LOGIC; + (*this)[ "std_logic_vector" ] = STD_LOGIC_VECTOR; + (*this)[ "string" ] = STRING; + (*this)[ "subtype" ] = SUBTYPE; + + (*this)[ "then" ] = THEN; + (*this)[ "to" ] = TO; + (*this)[ "transport" ] = TRANSPORT; + (*this)[ "type" ] = _TYPE; + + (*this)[ "units" ] = UNITS; + (*this)[ "until" ] = UNTIL; + (*this)[ "use" ] = USE; + + (*this)[ "variable" ] = VARIABLE; + + (*this)[ "wait" ] = WAIT; + (*this)[ "warning" ] = WARNING; + (*this)[ "when" ] = WHEN; + (*this)[ "while" ] = WHILE; + (*this)[ "with" ] = WITH; + (*this)[ "wor_bit" ] = WOR_BIT; + (*this)[ "wor_vector" ] = WOR_VECTOR; + + (*this)[ "xor" ] = _XOR; }