* New: In Hurricane, In Cell, add Placed and Routed flags to know the
state of the Cell.
* Change: In CRL Core, In ApDriver, do not save the RoutingPads as
external connectors if the design is *not* routed (create
conflics on reload with the newly generated RoutingPads).
* Change: In Etesian, set the Placed flag on the Cell.
* Change: In Kite, set the Routed flag on the Cell.
* Change: In Cumulus, in RSavePluginAll, save the layout only if it
has a bounding box.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
Use a structure based on a simple ring of NetAliasHook. The Net
holds a global map, sorted by names of all the aliases of all Nets.
Elements NetAliasesHook of the map are slaves of ring whose master
is an attribute of the Net (it is *not* in the map, as the primary
name of the Net).
In case of merge, the aliases of both Nets are merged and the
name of the merged one become an alias.
The Cell::getNet() looks in both the Net map and the aliases to
find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
configuration files so the real technology is read as early as
possible to set up the <gridsPerLambda> factor before any lambda
is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
a design into VHDL compliant names (mainly from Blif/Verilog).
This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
messages. Align the loading progress information on the other
parsers.
Add a capability to select which component of the design will
be returned, if there are more than one. Use the "." as separator.
For exemple you can request "Processor.Alu", which will load
the "Alu" component from the design in "Processor.blif".
To be able to save a Blif loaded design, systematically convert
all the name for VHDL compliance, as it is the format used by
the Coriolis native files (vst).
Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
Partly redundant with the previous one. Have to better organize
that later.
* Change: In Cumulus, in Configuration.py, in the horizontal & vertical
wire creation adds new flags ExpandWidth to draw wires one lambda
bigger than the minimal width (see ClockTree.py patch).
* Change: In Cumulus, In ClockTree.py, use non default width to draw
wires of the H branch of the clock tree. This is to prevent them
to be recognized as "manual global routing", which they are not
and not event topologically compatible.
* Bug: In Kite, in BuildPowerRails, change the way clocks are detected
when working on a single block (not a whole chip). Now look only
in clock which are external and do not filter out already routed
ones.
* Change: In KiteEngine, in createGlobalGraph(), systematically call
flattenNets() so nets that are added after the first flattening
in the placer are also flattened. The flattenNets() Cell method
takes care of not flattening twice a net.
* Change: In Bootstrap & ccb, the coloquinte project is renamed into
"importeds", it will be the home of all the externally
devellopped softwares that are needed to build Coriolis.
Add explicit support for Fedora ("Linux.fc") and uses
site-packages, as everybody else.
* New: In CRL Core, in etc/, adds the configuration files for Etesian.
* New: In Etesian, activate the Configuration object. Now uses it's
own configuration variables instead of borrowing those of
Nimbus & Mauka.
* Change: In Documentation, updated User's Guide to present Etesian
as the placer, instead of Mauka.
* Change: In Cumulus, slight change in ClokTreePlugin and ChipPlugin
to match the new Etesian/Python interface.
* New: In Hurricane, in DebugSession, add a new method to activate the
trace inconditionally with a certain level.
* New: In Hurricane, in HyperNet, allow copy construction as there is
no reason to disallow it and we need it now.
* New: In Hurricane, in Cell::flattenNets(), add a new option to prevent
the flattening of the clock net(s). For more safety perform the
DeepNet creation *outside* the Collection loop.
* Bug: In Hurricane, in Cell_HyperNetRootNetOccurrences, skip the
DeepNets because they are the result of another flattening operation.
* New: In Isobar, in PyBasicLayer, export C++ method getBlockageLayer().
* New: In Isobar, in PyRoutingGauge, export C++ method getLayerPitch(),
needed by Cumulus plugins.
* New: In Etesian, EtesianEngine::findYSpin() to look for the Y orientation
if some cells are already placed. Typically the buffers of a clock
tree.
Pass the correct orienation to row_compatible_orientation().
Do not try to add feeds in the ISPD05 benchmarks. For now the
benchmarks are detected through their names (unreliable).
* Change: In Knik, in KnikEngine::initGlobalRouting(), allow the clock
to be routed as an ordinary signal when the clock tree is not
used.
* New: In Kite, in BuildPowerRails, management & detection for the
pre-routed clock.
In KiteEngine constructor, early initialization of the blockage
net to avoid later troubles in BuildPowerRails.
* New: In Cumulus, in ChipPlugin, add support for Etesian plus new
configuration parameter 'clockTree.placerEngine' to select between
Mauka and Etesian.
* New: In Cumulus, in BlockCorona, add blockages in the vertical sides
in the vertical layer to prevent the router to use the vertical
tracks in under the prower lines (for example, blockage in M3
with power line M5).
In Cumulus, in ChipConf add attribute to access the blockage net.
* New: In Cumulus, when the clock tree is disabled, do not generate
the last rail around the block (the clock rail).
* Bug: In Cumulus, in ChipConf use the clock pad to guess the clock
signals and *not* the power pad.
Add more meaningful error messages if a pad global signal is
not found (implicit connexion by name).
* Bug: In Cumulus, in ClockTree, compute correctly the cells Y spin,
that is *from the bottom of the cell AB* (not from 'zero').
* Bug: In Bootstrap, in coriolisEnv.py, check if devtoolset-2 is already
active before launching it as a sub-shell.
* Bug: In Isobar, In PyHurricane.h, DBoDestroyAttribute() set the proxy
pointer toward the C++ object to NULL. So when the Python object is
deleted no double-deletion occurs on the C++ object.
Add some more trace information in Python link/dealloc.
* Change: In CRL Core, in cyclop, make CMakeLists.txt automatically
choose the right rule for linking the binary wether we use Qt 4 or
Qt 5. Very irksome problem.
* New: In EtesianEngine::addFeed(), do not take into account instances
that are not placed entirely inside the top cell abutment box (was
causing a core dump).
* Bug: In Katabatic, in GCellQueue, correct a mismatch between a GCell
set and the iterators used upon it.
* Bug: In Mauka, in Row & Surface correct a mismatch between a container
and it's iterator.
* New: In Etesian, updated to work with the latest Coloquinte, patch
contributed by G. Gouvine.
Added EtesianEngine::setDefaultAb() to compute an abutment box if
the Cell is completly unplaced.
* New: In cumulus, in ClockTree, now the placer can be configured to be
either Mauka (slow simulated annealing) or Etesian (fast analytic).
New setting 'clockTree.placerEngine' in plugin settings.
* New: In Bootstrap, in Builder & coriolisEnv.py support for RHEL7/SL7.
The sub-directory name is 'el7_64'.
In qt_setup() add QtSvg to list of Qt5 & Qt4 used libraries.
* New: In Hurricane, In Cell add a placeholder for flags. First use to
store whether the Nets have been transhierarchically flatteneds.
* New: In Hurricane, In NetRoutingState add an Unconnected flag for
more accurate diagnosis.
* New: Hurricane, in CellViewer add an entry menu for stress tests.
The script must be named "stressScript.py" in the cwd.
* Change: In CRL Core, in display.conf add a scaling parameter for the
display threhold of the layer. This way we can adapt to different
standard cells height.
* Change: In CRL Core, in ISPD05 bookshelf loader, use the pitch of the
cell gauge instead of a hard-wired 5.0.
* Change: In Cumulus, in ClockTreePlugin, add support for Etesian placer
and a new configuration parameter to choose between Mauka/Etesian.
* New: In Etesian, support for the latest Coloquinte.
Add feed insertion stage.
* Bug: In Kite, In BuildPowerRails, check that _ck is not NULL before
tring to access it's name...
* Change: In Kite, check if the Cell has it's Nets flattened before
doing it (or not).
* Bug: In Cumulus, in ClockTree.py, do not use "tie_x0" which is 2 pitch
wide to fill the free space left by clock-tree removed (unused)
buffers. If the buffer size width is odd (in pitch), it will left
a gap in the WELL. That was the cause of DRC notch errors.
Instead use "rowend_x0" which is one pitch wide.
Should use the same mechanism as in Mauka InsertFeed.
* Change: In Hurricane, the NetRoutingProperty is moved into Hurricane
from Katabatic. Needed for Knik to be able to access thoses
informations.
* Change: In Hurricane, in RoutingPad::setOnBestComponent(), now in
case of identical area, select the component of lowest id.
This should not be needed if the component ordering was fully
deterministic as it should be (will investigate later).
This is to ensure that the choosen component is always the
same, especially between save/load of a global routing.
* Bug: In Katabatic, in AutoContactHTee::updateTopology(), invalidate
the segments only if the topology is valid (no NULL in the
cached segments).
* Bug: In Katabatic, in GCellTopology::construct(), throw an error
if the topology is bad instead of trying to continue (and core
dump later... ).
* Bug: In Kite, in BuildPowerRails, distinguish the name of the master
net in the pad (for vddi, vssi, vdde, vsse, ck, cki & cko) and the
name of the net in the *chip* netlist. Must use the later to make
comparison as they may differs.
* Change: In Knik, in save/load solution, exclude nets that are not
globally routed by Knik. That is which NetRoutingProperty is not
*Automatic*.
* Bug: In Cumulus, in chip.BlockPower take account of the layer
width extention to sligthy shrink the connector thus avoiding a
notch with standart cell in some cases.
* Change: In Cumulus, in chip.ClockTree disable the use of fixed Steiner
trees for the leaf clocks, as it seems overconstrained for the
router. First move was to lower them in M2/M3 (instead of M3/M4)
but that was not sufficent.
* New: In Cumulus, RSavePlugin for recursively saving a physical
hierarchy.
* New: In documentation, first embryo for RDS file. Should have been
in Alliance git, but I prefer to keep newest doc in Coriolis.
* Bug: In Katabatic, in AutoContactTurn::cacheAttach() unset the
"cache invalidated" flag *only* if the h1 & v1 component are
sets. This is needed because we can attach *before* the first
cache revalidation (in the initial building stage).
* Bug: In Katabatic, in AutoSegment::getPPitch() out of bound access
of the top of the RoutingGauge, in case of a top layer segment
with a spin top flag (maybe this shouldn't happen?).
* Change: In Kite, in SegmentFsm::conflictSolveByPlaceds() take
account as conflicting other global, global, blockage *and*
now fixeds.
* Change: In Cumulus, in px2mpx.py more accurate way of transforming
the pad blockages.
* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
variable to define the pad model name extension ("px" for "sxlib
and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
of used for power & clock supply. We may remove the extention in
the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
longer place the accessing contact *at the center* of the
RoutingPad. It works under sxlib because buffers & registers all
have same size terminals. But this is not true under vsxlib,
leading to misaligned contacts & wires. Now systematically place
on the slice midlle track (maybe with one pitch above or below).
This is still very weak as we do not check if the terminal
reach were the contact is being put. Has to be strenthened in
the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
of PyInt for DbU conversions. In PyHurricane argument converter,
automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
in case of discrepency in global net connections (i.e. no net
of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
model name to find "pck_" or "pvddeck_", do not compare the
extension part. But we still use hard-coded stem pad names,
maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
RoutingPads of fixed nets, they are already through the
BuildPowerRails stage (and it's causing scary overlap warning
messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
deep-plug when the core is flat (not sub-modules). All the new
nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
that the core is aligned on the GCell grid (i.e. the slice
grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
while looking for the bigger N-E RoutingPad. Forgot to decrement
the index...
* Bug: In ClockTree plugin, only the logical view of the clock buffer
was loaded, so no external components where found on the I/O nets.
The external components are loaded only when the *physical* view
is loaded. Didn't show on sxlib because the buffer was fulled
loaded *before* running the ClockTree.
* Bug: In PyHurricane, in the various LocatorNextMethod() macros,
sometimes an empty collection can be returned by Hurricane
(GenericCollection()), which has a NULL locator. So check
if the locator is *not* NULL before trying to access it...
* Change: In Chip, more accurate error messages related to the clock
detecttion.
* New: In ClockTree plugin, select the name of the buffer cell through
configuration (parameter: "clockTree.buffer"), and guess the I/O
name of this buffer automatically.
Put configuration parameters in plugin.conf and not mauka.conf.
Bug: strangely triggers a coredump in components collection
when used with <vsxlib>. Some debug printing still active until
that is solved.
* New: In Chip plugin, make the size and numbers of the block rails
configuration parameters (in plugin.conf).
* Change: In Hurricane, in Plug::setNet(), more informative error messages.
* Change: In Hurricane, In Segment, more informative error messages.
* Change: In Hurricane, In DeepNet, accessor for the Net occurrence.
* Bug: In Katabatic, in AutoSegment::create(), error message uses correct
variables (vertical was using horizontal)...
* Change: In Kite, in BuildPowerRails, already existing wiring in instances
is copied up as blockage. Uses blockage layer instead of true layer
(it was a bug).
* Change: In Kite, in BuildPreRouted, consider as manual global routing
nets with only default wiring (default size wire & contacts).
Non-default routing is flagged as fixed (with the NetRoutingState
property).
* New: In Cumulus, first versions of the ClockTree and Chip plugins.
Clock Tree plugin:
- It is strongly advised to use have 4 metal routing layers for the
tree to work. Otherwise, problems can arise with the detailed
routing (fully obstructed terminals).
- H-Tree can only be build (for now) for design with a form factor
between 0.5 an 2.
- The tree is created at the block top-level and only the leafs are
trans-hierarchically created on the instances/models. The new
cell with a clock tree, along with all it's sub-models is created
with a "_clocked" suffix.
- Leaf cells are connected through a simple Minimum Steiner Tree.
- Shorts are avoided by a systematic shift of the wires according
to their kind. No wire must pre-exist. When used as a sub-module
of "chip" the wires cannot be moved. When created on a block,
the wires can be loaded in the detailed router as manual global
router.
Chip Plugin:
- Perform the pad placement and corona creation. Replacement at
last of the clunky code from Wu Yifei.
- Relies on a Python configuration file '<design>_chip.py' with
a "chip" dictionnary.
* New: In Cumulus, new Alliance.py module (*not* a plugin) providing
an encapsulation for Alliance command line tools. The other main
feature is that it provides a "Makefile like" behavior. Based on
the command dependencies a DAG is contructed, then a static
ordering of the commands. Commands are then executed to rebuild
outdated target.
The Alliance environment supplied to the commands is read from
the Coriolis configuration file <alliance.conf>.
For this first evaluation version, only <boom>, <boog> and
<loon> support are provided.
It still not clear how to encapsulate the Coriolis tools in
the same way.
* Change: In CRL Core, in helpers/__init__.py, change the way the static
initialization (module) is done. All the commands are put inside
a "staticInitialization()" function, which is then explicitly
called by others. This is a better solution agains *no* or *twice*
initialization. Modificate <coriolisInit.py> accordingly (as
<Alliance.py> from Cumulus.
Finally get rid of the demonic code from Wu Yifei...
* New: In Isobar, added encapsulation of Interval (don't know how have
forgotten it for so long).
* Change: In Isobar, In PyLayer, new PyLink_LayerDerived() function to
create/link the C++ object to the correct derived class and not the
base one (PyLayer) which then prevent to use the specialized methods.
Must replace PyLink_Layer() througout all the code.
* Change: In Isobar, in PyPoint the "setX()" & "setY()" methods where
still capitalized.
* Change: In Isobar, in PyQuery, complete the exportation of the C++
interface. remove the code belonging to a more "boost" way of
building the Python interface (will do that in a far future).
* New: In CRL Core, In PyAllianceFramework, export isPad() method.
* Change: In Unicorn, in unicornInit.py, protect the loading of each
single plugin by a "try" / "except" clause to the failing of one
plugins do not stop the loading of the next one.
Pass the same dictionnary argument to unicornHook() as for
ScripMain(), this is more uniform this way.
* New: In Cumulus, complete replacement of the chip placement scripts
from Wu Yifei (at last!). The clock-tree integration is still to
be done.
________________________________________________________________________
* New: In all to CMakeLists.txt, disable the warning about deprecated
WIN32 under cygwin.
* New: In boostrap, in ccb.py, coriolisEnv.py and builder/Configuration.py
add recognition in uname for the values returned under Windows/Cygwin.
* New: In Documenation, in UsersGuide.rst add some informations about
Cygwin and a section for the devel branch.
* Change: In Isobar, the Python interface was not exactly mirroring the
C++ one, now it is the case. The Python code should look likes almost
exactly like the C++ one, the only differences remaining being due
to the languages respective syntaxes. Note that in the case of
constructor functions, it leads to a slightly longer notation in
Python that it could have been (mimic the ".create()" static
member). Main modifications:
1. Mirror the static constructor syntax with create():
Cell( ... ) ==> Cell.create( ... )
2. Correct hierarchy for constants in Instance, Net, Pin
& Transformation. For example:
Hurricane.PlacementStatusFIXED
==> Hurricane.Instance.PlacementStatus.FIXED
Hurricane.OrientationID
==> Hurricane.Transformation.Orientation.ID
Hurricane.TypeLOGICAL ==> Hurricane.Net.Type.LOGICAL
Hurricane.DirectionIN ==> Hurricane.Net.Direction.IN
* Change: In CRL Core, correction to match the improved Python API
in the configutation helpers.
* Change: In Cumulus, correction to match the improved Python API.
* Change: In Stratus, correction to match the improved Python API.
* Change: In Documenation, update for the new Python interface
(both user's guide & examples).
* Note: We must port those changes into Chams for it to continue
to run.
* Change: In Documenation, update the Python script support part.
* New: In Hurricane, in CellViewer, create a simpler API to graft menu
and actions into the menubar. Mainly addToMenu() which take care of
the QAction creation but also locate the relevant QMenu, base on
the Qt object name. Regroup all the widget & action creation inside
the body of the constructor, this way almost all actions can be
removed from the attributes of the CellViewer.
addToMenu() is supplied in three flavors:
1. For C++ callbacks in GraphicToolEngines (with a binded
member function method).
2. For running Python scripts to be used by the plugin system.
3. To insert separator in menus (to give a more homogeneous
look).
Remove the last remnants of Stratus scripts (unificated with basic
Python scripts).
* New: In Hurricane, in PyCellViewer, export the interface to graft
Python scripts into the CellViewer menu tree.
* Change: In Etesian, in GraphicEtesianEngine, use the new API to
graft menus & callbacks into the CellViewer.
* Change: In Mauka, in GraphicMaukaEngine, use the new API to
graft menus & callbacks into the CellViewer.
* Change: In Kite, in GraphicKiteEngine, use the new API to
graft menus & callbacks into the CellViewer.
* New: In Cumulus, install Python scripts as plugins for Unicorn under
<PYTHON_SITE_PACKAGES>/cumulus/plugins/.
* New: In Unicorn, in UnicornGui, make uses of the new API for creating
menus in the CellViewer. Creates the stem menu for the P&R tools.
Add a Python initialization mechanism to read the plugins
installeds into <PYTHON_SITE_PACKAGES>/cumulus/plugins/.
Miscellaneous:
* Change: In <crlcore>, in display.conf use the same display threshold
for both METAL2 & METAL3.
In alliance.conf, the side of VIAs in the gauge is 2l (not 3l).
In kite.conf, separate edge densities for H/V.
* Change: In <Cell>, in flattenNets() use flag as argument, not a
boolean. Do not create rings for clock or supply nets.
* Change: In <DeepNet>, in _createRoutingPads() do not create rings
for clock or supply net (duplicated policy as in Cell::flattenNets()).
* Bug: In <ControllerWidget>, at last find the bad signal disconnect
that was causing ungraceful messages.
* Change: In <knik>, in Edge display occupancy/capacity in the string
name. Improved display progress and debugging capabilities.
Improved exception catch & breakpoint managment:
* Bug: In <PaletteWidget>, in updateExtensions() replace the calls to
deleteLayer() by delete. This cause the widget to be immediatly
erased instead of waiting for the event queue to be completly
processed. This was causing the widget to be left in a incoherent
state when stoping at a breakpoint.
* Bug: In <BreakpointWidget>, in execNoModal(), flush the main event
loop (QApplication::flush()) *before* lauching the *local* event
loop. This is to ensure all widgets are in their final state when
waiting (especially <PaletteWidget>).
* Change: In <ExceptionWidget>, new method catchAllWrapper() to
execute any std::function< void() > function/method with a "try"/
"catch" wraparound and lauch the widget in case something is catch.
* New: In <hurricane>, support for a oberver pattern, backported from
<katabatic> with an Obervable capable of being linked to any
number of Obervers.
* New: In <Cell>, made it observable to detect Cell change, currently
emit two kind of signals:
- Cell::CellAboutToChange : *before* any change.
- Cell::CellChanged : *after* the change has been completed.
* New: In <UpdateSession>, in Go::invalidate() add the Cell owning the
Go to the UPDATOR_STACK (of course the cell is added only once).
In addition, when the Cell is added, send a notification of
Cell::CellAboutToChange to all it's observers. The slave instances
are also invalidated.
Conversely in UpdateSession::_preDestroy() for each invalidated
Cell send a Cell::CellChanged notification to all observer.
The UPDATOR_STACK has been slightly amended to accept Cell which
are not Gos. Prior to this, the Cell where completly excluded from
the UpdateSession mechanism, so it's instances where never actualised
of anything referring to the Cell for that matter.
Note: we use two different mechanisms to transmit a Cell change,
observers and the slave instance map. I think at some point it
should be unificated.
* Change: In <CellViewer>, make it a Cell observer to redraw when the
cell is modificated (also update the palette).
Uses the catchAllWrapper() to protect all critical actions.
* Change: In <GraphicTool>, no longer need of cellPreModificated and
cellPostModificated signals. Now done through the Cell obersvers.
* Change: In <mauka>, <etesian> & <kite> now uses the catchAllWrapper
method for protection (need to split methods in two, to be able
to pass it as argument). No longer emit cellPreModificated and
cellPostModificated.
Support for RoutingGauge in P&R:
* Bug: In <placeandroute.py>, the connection from the internal power
ring to the connectors was not done correctly. Wrong contact layers
leading to a gap.
* Change: In <BuildPowerRails>, detection of the corona signals based
on how the "pck_px" pad is connected. No longer based on name
matching.
* Change: In <placeandroute.py>, support for 2 routing metal only
(3 metal in the technology).
* Change: In <katabatic> & <kite> support for a "top layer" limitation
on the routing gauge, this allows to use only two routing metals
(METAL2 & METAL3). Work in progress.
Details:
* New: in <bootstrap>: add support for devtoolset-2 in ccb. Run the
cmake commands through 'scl', set shell environment variables
BOOST_INCLUDEDIR & BOOST_LIBRARYDIR and disable the default
system path search.
* Change: In various flex scanners add the %nounput to suppress
compiler warnings.
* Change: Little cleanup for g++ 4.8.1 as it's more strict.
* Change: In various top CMakeLists.txt, suppress extraneous '/'
after DESTDIR.
Project hierarchy reorganisation:
* With svn, we were doing a tool by tool checkout, suppressing the
whole repository hierarchy level.
* The tools were also grouped, inside one repository, into multiple
projects (<bootstrap>, <vlsisapd>, <coriolis>).
* We do not want to split up each tool into a separate repository,
given their tight integration (except for vlsisapd).
* We choose to simplify, and consider all tools in a svn repository
one project. Due to the way Git clone repositories, the directory
containing the project is now to be seen under "src/".
CMake modifications:
* Now that the <vlsisapd> and <bootstrap> projects are merged into
coriolis, modificate the top CMakeLists.txt of each tool to uses
only Coriolis (and bootstrap hard wired).
CCB compile script modifications:
* Uses the new source tree hierarchy, with the project directory
inserted.
* Remove (comment) all parts relateds to svn managment.
* Git is sufficiently simple so that we do not want to integrate
command shortcut into the script.
SVN cleanup:
* Remove the obsolete <chamsin> tool, that has become the full fledged
<chams> project long time ago.
- New: Added FreeBSD/Ubuntu patches from Otacilio De Araujo
(<otaciliodearaujo@gmail.com>).
* ./cumulus:
- Change: In placeandroute.py, raise ErrorMessages (from crlcore) instead
of deprecated strings.
- Change: In pyRouteCk, the clock grid now systematically covers the core
area instead of only the area where clock signals are useds. This is
to alleviate the constraint of alignement on the pvsseck pads (they
must be in direct regard of the clock grid).
- Bug: In placeandroute.py/createGrid(), VIAs of the big clock grid must
have the same width as the wires (12l). But due to the layer extension
the VIA side must be of 11l.
- Bug: In placeandroute.py/createGrid(), wires connecting cell clock pin
to the clock trunk must respect the preferred routing direction.
The only exception being when the wire is completly enclosed under
the trunk wire. This is for the obstacle stage of the detailed router.
- Change: For the setup_sysconfdir() boostrap/cmake macro uses the
CMAKE_INSTALL_PREFIX to guess where we are being installed.
Should be more reliable than any *_TOP environment variable.
- Bug: Uses correct Contact with for rings.
- Bug: Reorder import so that CRL is always imported first so that the
problem of duplicated type_info RTTI doesn't show.
- Change: New problem identified with the Python modules: each module seems
to be built as a complete binary, so all the static C++ initializers are
allocated in each module. In particular the C++ tree inheritance is built
for *each* module so we cannot longer uses the typeid() comparisons
across modules... It was used by boost::program_options to perform is
casts with boost::any and was starting throwing exceptions because of
bad casts. program_option was first initialized in "configuration"
first included by PyViewer then in PyCRL (see Utilities.cpp).
A first solution is to re-order the import of Python modules in
stratus1/st_model so that CRL is imported first.
The second is to not not link "configuration" with boost::program_option
as only the binary vlsisapd-conf-editor needs it.
That is a serious problem of which we must be aware and can cause further
strange behaviors.
Debug code used to diagnostic has been kept commented in the sources a
it may be needed again :-(
This behavior do not affect our singletons because they are part of
dynamic libraries that seems to be correctly shared between the various
Python modules.
* ./stratus1,
./cumulus:
- Change: Replace calls to CRL.getAllianceFramework() by CRL.AllianceFramework.get().
Jean-Paul Chaput
Sophie Belloeil