* New: In CRL Core, in RoutingLayerGauge, adds a new parameter "obstacleDw".
It represents the distance to add from the *edge* of a blockage segment
to the next *axis* of a routing track. This was previously computed as
the pitch minus the mimimum half wire width. This works if the pitch
is *equal* to the wire width plus the minimal distance (edge to edge).
But if the wire width is less, than it leads to too great a distance
around obstacles, making them bigger than they are. And potentially
blocking everything. To summarize:
before: obstacleDw = pitch - wireWidth/2 (deduced)
after: obstacleDw = explicitly setup, usually:
pitch - max(wireWidth)/2
Modify the Alliance configuration helper and the various kite.conf
file accordingly.
* New: In Kite, in BuildPowerRails, make use of "obstacleDw" to compute
the footprint of a blockage.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
Use a structure based on a simple ring of NetAliasHook. The Net
holds a global map, sorted by names of all the aliases of all Nets.
Elements NetAliasesHook of the map are slaves of ring whose master
is an attribute of the Net (it is *not* in the map, as the primary
name of the Net).
In case of merge, the aliases of both Nets are merged and the
name of the merged one become an alias.
The Cell::getNet() looks in both the Net map and the aliases to
find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
configuration files so the real technology is read as early as
possible to set up the <gridsPerLambda> factor before any lambda
is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
a design into VHDL compliant names (mainly from Blif/Verilog).
This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
messages. Align the loading progress information on the other
parsers.
Add a capability to select which component of the design will
be returned, if there are more than one. Use the "." as separator.
For exemple you can request "Processor.Alu", which will load
the "Alu" component from the design in "Processor.blif".
To be able to save a Blif loaded design, systematically convert
all the name for VHDL compliance, as it is the format used by
the Coriolis native files (vst).
Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
Partly redundant with the previous one. Have to better organize
that later.
* Change: In CRL Core, simplify the loading sequence. The technology,
both symbolic and real is now loaded directly from coriolisInit.py
and not through the Alliance loader. This was a leftover from the
time configuration was in XML. Remove others traces of XML loading.
Remove SYMB_TECHNO_NAME, REAL_TECHNO_NAME & DISPLAY from the Alliance
environement, as they was no longer used.
Note that technology *still* need to be loader *after* Alliance
framework has been initialized.
Gauge information is moved from <alliance.conf> to <kite.conf>.
* Bug: In Coloquinte, in optimization_subproblems.cxx static variables
must not be inlined. Generate a problem when linking in debug mode
(seems the symbol gets optimised out).
* Bug: In Katabatic, in Grid::getGCell(), when the coordinate is *outside*
the area, do not try to find a GCell, directly return NULL.
* New: In Unicorn, create a generic command launcher named "coriolis" which
automatically take cares of all environement setup, then run a command
by default, it's <cgt>, but it can be anything. For example: <zsh>.
* Change: In Bootstrap & ccb, the coloquinte project is renamed into
"importeds", it will be the home of all the externally
devellopped softwares that are needed to build Coriolis.
Add explicit support for Fedora ("Linux.fc") and uses
site-packages, as everybody else.
* New: In CRL Core, in etc/, adds the configuration files for Etesian.
* New: In Etesian, activate the Configuration object. Now uses it's
own configuration variables instead of borrowing those of
Nimbus & Mauka.
* Change: In Documentation, updated User's Guide to present Etesian
as the placer, instead of Mauka.
* Change: In Cumulus, slight change in ClokTreePlugin and ChipPlugin
to match the new Etesian/Python interface.
* New: In Bootstrap, in Builder & coriolisEnv.py support for RHEL7/SL7.
The sub-directory name is 'el7_64'.
In qt_setup() add QtSvg to list of Qt5 & Qt4 used libraries.
* New: In Hurricane, In Cell add a placeholder for flags. First use to
store whether the Nets have been transhierarchically flatteneds.
* New: In Hurricane, In NetRoutingState add an Unconnected flag for
more accurate diagnosis.
* New: Hurricane, in CellViewer add an entry menu for stress tests.
The script must be named "stressScript.py" in the cwd.
* Change: In CRL Core, in display.conf add a scaling parameter for the
display threhold of the layer. This way we can adapt to different
standard cells height.
* Change: In CRL Core, in ISPD05 bookshelf loader, use the pitch of the
cell gauge instead of a hard-wired 5.0.
* Change: In Cumulus, in ClockTreePlugin, add support for Etesian placer
and a new configuration parameter to choose between Mauka/Etesian.
* New: In Etesian, support for the latest Coloquinte.
Add feed insertion stage.
* Bug: In Kite, In BuildPowerRails, check that _ck is not NULL before
tring to access it's name...
* Change: In Kite, check if the Cell has it's Nets flattened before
doing it (or not).
* Change: In CRL Core, in Alliance.py, no longer requires the
configuration file to uses symbols from CRL.Environment or
CRL.RoutingLayerGauge. This way the <alliance.conf> file can be
parsed by a different parser.
In <alliance.conf>, for the various technologies, make uses
of the new C++ independent constants.
* New: In CRL Core, in helpers/__init__.py, provide a "Dots" class
(rewrite the C++ one in pure Python).
* Change: In Kite, Katabatic & Knik, express the number of tracks truly
available to the global router by the number of tracks reserved to
the local routage inside a GCell. Replace the ratio parameter
"hEdgeCapacity" by an integer parameter "hTracksReservedLocal"
(duplicate for verticals).
It is more explicit to give directly the number of tracks that
are to be used locally, and potentially saves us from rouding
problems when calculating the number of availables tracks.
Note: we cannot do that for the layer saturateRatio as it
uses the density ratio that take account local wires, leading
to fractional results.
* Change: In Katabatic, in <GCellGrid>, rename checkEdgeSaturation()
into checkEdgeOverflow(), more explicit.
* Change: In Knik, in <Graph>, display the computed capacities of the
lower left node edges (should be the same througout all the grid).
* Change: In Unicorn, in <cgt.py>, uses the new parameters names for
edge density.
Placement management:
* Change: In <metis>, always disable the hMetis support regardless of
it being detected or not as the placer is still unable manage the
final bin contents.
Routing gauge management:
* Bug: In CRL Core, <vsclib/alliance.conf>, set the correct pitches and
size for the routing layers and the cell gauge.
* Change: In Katabatic & Kite, extract the correct extension cap for each
routing layer from the layers characteristics (cache then in
Katabatic::Configuration).
* Change: In Katabatic, <AutoSegment>, create segment with the wire width
defined in the gauge. For AutoSegment created on already existing
Segment from the global routing, adjust the width.
* Change: In Katabatic, <AutoSegment>, more accurate information about how
a segment is connected to terminal via source and/or target.
The flag SegStrongTerminal is splitted into SegSourceTerminal and
SegSourceTarget (but still used as a mask). So now we can know by
which end an AutoSegment is connected to a terminal.
* Change: In Katabatic, ::doRp_Access(), create constraint freeing segments
not only when HSmall but also when VSmall (more critical for <vsclib>).
Otherwise we may see AutoSegments with incompatible source/target
constraints.
* Change: In Kite, BuildPowerRails, do not create blockage on PinOnly
layers *but* still create power rails planes. This is a temporary
workaround for <vsclib> where the METAL1 blockages overlaps the
terminals (it was fine for Nero, but they shouldn't for Kite).
* Change: In Kite, <RoutingEvent>, if a TrackSegment is overconstrained,
directly bybass it's slackening state to DataNegociate::Slacken.
Also rename the flag "_canHandleConstraints" to "_overConstrained",
seems clearer to me.
Miscellaneous:
* Change: In CRL Core, <Utilities>, add a "pass-though" capability on the
mstream to temporarily make them print everything.
In CRL Core configuration files, "display.conf", "patterns.conf" and
"technology.conf" share most of their code. So that common part is put
into "common/" and sourced from the final configuration file.
Update the documentation according the the new initialization scheme.
In CRL Core, the layout of the files under "/coriolis2/etc" changes.
Instead of having them directly under "etc", they are now replicated,
in subdirectories. Each subdirectory having the name of the associated
symbolic or real technology (they are kept separated). We have, for
now:
* etc/cmos/ : symbolic, the Alliance original one.
* etc/vsc200/ : symbolic, for G. Petley vsclib.
* etc/hcmos9/ : real, generic fake (130nm).
To tell which pair (symbolic,real) technologies must be used we create
a *second* (sigh) configuration file "coriolis2_techno.conf", and it's
hidden counterpart in the user's account, to set it up. It needs to be
separate because it is read as early as possible and select which set
of configuration files would be read.
Also add support up to METAL8 and POLY2 in CRL core and it's Alliance
parser/drivers.
Jean-Paul Chaput