* Bug: In Hurricane, in tstream (Commons.h), in the *template* overload of
operator<<(), do not use the operator<<() of ostream as it will be
looked up in "stage 1" (template definition) and so will miss all the
overloads added later and built over getString<>(). Instead, make use
of getString<>(), which, as another template will be looked up in
"stage 2" (template instanciation) and at that point will have all the
needed template specialisation of getString<>().
We also need to define new stream manipulators to be able to create
a matching template overload not dependant from the implementation.
To avoid name clashes, we prefix a 't'. For now, only 'tsetw()' is
refined.
As a side effect, we cannot directly print bit-fields into the stream,
we must go through an intermediate variable (happens once in AutoContact).
* Change: In Hurricane Commons.h, even when cdebug print nothing, it slow
down the program (three times for Kite!). Create a macro cdebug_log
which calls cdebug *only* if the debug level is active.
* Change: In Hurricane, in Flags add operator overload for "int" type
and not only "unsigned int". Otherwise the compiler complaints about
ambiguous overload when using enum values which are considered as
"int".
Simpler code for the BaseFlags::contains() method.
Added implicit conversion from BaseFlags toward bool type.
* Change: In Hurricane, in Commons, complete replacement of the previous
two trace systems (trace & ltrace) by a stream-based one.
As it is a true object it is much less fragile than the one based
on defines (but maybe a little slower).
Define a reservation table for the trace levels for all the
Coriolis & Chams components.
* Change: All tools, use the new trace system.
* In Katabatic, in GCellConfiguration, added support to 3G_2M2 (generic).
* In Katabatic, in GCellGrid, in getUSide() we were not using the correct
contant set (Constant namespace instead of Kb...) so the size returned
was always X. It doesn't show if the chip is square...
* In Kite, in Track::getBeginIndex(), if the position requested was enclosed
in same net segments, we were going one index too far in the "previous"
direction.
* In Kite, in Track::getOverlapBounds() we where going one index too far
in the "next" direction while computing the "end" index.
* New: In CRL Core, in RoutingLayerGauge, adds a new parameter "obstacleDw".
It represents the distance to add from the *edge* of a blockage segment
to the next *axis* of a routing track. This was previously computed as
the pitch minus the mimimum half wire width. This works if the pitch
is *equal* to the wire width plus the minimal distance (edge to edge).
But if the wire width is less, than it leads to too great a distance
around obstacles, making them bigger than they are. And potentially
blocking everything. To summarize:
before: obstacleDw = pitch - wireWidth/2 (deduced)
after: obstacleDw = explicitly setup, usually:
pitch - max(wireWidth)/2
Modify the Alliance configuration helper and the various kite.conf
file accordingly.
* New: In Kite, in BuildPowerRails, make use of "obstacleDw" to compute
the footprint of a blockage.
* Change: In Hurricane, in DataBase::CellDepths() the recursion stop
criterion must be Cell::isLeaf() and not Cell::isTerminal() as
the second one can be used to hide some levels of hierarchy,
and we want all of them in a blob.
* New: In Hurricane, in Cell, create a new Slaveds relation to keep
track of all the Cells with a slaved abutment box. This work is
incomplete as we do not manage the behavior in case of merge or
Cell destruction or slaving Cells with aready slaveds ones.
Modify Cell::setAbutmentBox() to work in both autonomous and
slaved mode.
* New: In Hurricane, in Net, add a new type of Net: BLOCKAGE this
avoid us to be dependant on the framework pattern recognition.
(change propagated to the Python support)
* New: In CRL Core, in the various drivers, recognize blockage nets
as such and set their type accordingly.
* Change: In CRL, in Toolbox::deleteEmptyNets(), preserve blockage
Nets. This was the cause of crashs in Kite::BuildPowerRails() as
we where trying to use a deleted blockage net...
* Bug: In Hurricane, in NetAlias, do not write NetAlias as a name
but as a type. They were not read back and moreover staying in
the JSON parser stack.
* Bug: In CRL Core, in BlifParser, recognize clocks (Alliance patterns).
* Change: In Cumulus, in RSavePlugin, "kw" manage a new "views" to
specify which views must be saved. Physical by default, but sometimes
we need logical as well. If the design contains uniquified cells,
save the logical view.
In ClockTree, abort the clock tree building if the design has no
top level clock.
* Change: In Katabatic, in GCellTopology, adds 2G_5M1 configuration.
* Bug: Kite, in BuildPowerRails, if we are not in a chip the nets
composing the H-Tree must be protecteds be blockages.
* Bug: In Hurricane, in HApplication, ExceptionWidget ans PyHurricane.h,
forgot to catch the Hurricane::Bug exception which was leading to
terminate() without explanations.
* Change: In Katabatic, In GCellTopology, now support one GCell with
five metal1 terminal of the same net. This unlikely configuration
did appear in the SNX for the first time...
* In Katabatic, in AutoSegment::canMoveUp(), adds the ability to reject
the move up if the density of the depth we comes from is below 0.6
in all the GCells, activated with the KbChecklowDensity flag.
* In Katabatic, In LayerAssign, new method moveUpNetTrunk2() which,
unlike the previous one, move up only the part of the Net trunk
which is connex to the seed segment. Use the canMoveUp with
low density checking to avoid unbalancing higher metal layers.
* In Kite, in SegmentFsm, use the canMoveUp() with low density checking.
* Bug: In Hurricane, in Cell::flattenNets(), addition to the topHyperNets
vector was done *inside* the components loop, resulting in multiple
additions of the same top net. This was leading to the RoutingPads
created multiple times on the same connectors. Hence the conflict in
KiteEngine::protectRoutingPads().
* Change: In Hurricane, in Cell::flattenNets(), do not create RoutingPads
or build rings on already routed Nets. A Net is considered already
routed if it has at least one Segment. This way we avoid Rubbers to
be drawn over routed Nets.
* Change: In Hurricane, in DeepNet, do not build RoutingPads & rings on
already routed Nets (same condition as in Cell::flattenNets()).
* New: In Hurricane, in HyperNet, new collection of all component
occurrences of an HyperNet. May or may not (default) include
components from the leaf cells.
* New: in Katabatic, in AutoSegment, recognize segments that are U-turn.
That is, based on two turn Contacts and going both top or bottom.
* New: In Kite, manage one pitch U-turn by making them diseapear from
the tracks. And make them same-metal when saving. Add a pack stage
to try to compact U-turn.
* Change: In Katabatic, in GCellTopology::doRp_AccessPad(), if the supporting
RoutingPad is big (more than two pitch), do not put the access
contact in the center but on the edge. This is to avoid cut violations
between the VIAs and the matrix of VIAs that may be generated under the
RoutingPad itself.
* Change: In Kite, in TrackSegment destructor, if the legnth of the wire,
without extensions is less than one picth, enlarge it so it encompass
it's source & target VIAs (to avoid notches).
* Bug: In Kite, in Track destructor, the TrackElements where detacheds,
but not deleted, causing a memory link.
* Change: In vlsispad, in Dots, add an enable/disable flag because when printing
into a cmess, it is only the base class ostream which is took into account
as none of it's methods are virtuals (silly me).
* Bug: In Etesian, print into cmess instead of cout and make use of the Dots
enabling feature.
* New: In Katabatic, added AutoContact::migrateConstraintBox() to transfert
constraint from one contact to another.
New flag for AutoContact, CntWeakTerminal for AutoContact which are at
the other of a segment directly connected to a terminal. They may hold
special constraints in case of caged terminals (computed in Kite).
In AutoHorizontal & AutoVertical, in ::_makeDogleg(), transfert flags
and constraints when breaking a segment directly connected to a terminal.
* New: In Kite, in protectCagedTerminals(), uses cross constraint on the
AutoContact opposite to the ContactTerminal (CntWeakTerminal) instead
of moving up one terminal over two consecutives. This is simpler without
degrading the routing quality.
* Change: In Knik, in Vertex, add a "blocked" flag to signal disabled
vertexes in the grid (must not be used by the global router).
Modificate the Graph::getVertex() method so that when a vertex
is geometrically queried, if is a blocked one, return a non-blocked
neighbor. This mechanism is introduced to, at last, prevent the
global router to go *under* the pad in case of a commplete chip.
* New: In Katabatic, in AutoSegment, a new state has been added: "reduced".
A reduced segment is in the same layer as it's perpandiculars.
To be reduced, a segments has to be connected on source & target to
AutoContactTurn, both of the perpandiculars must be of the same layer
(below or above) and it's length must not exceed one pitch in the
perpandicular direction.
To reduce an AutoSegment, call ::reduce() and to revert the state,
call ::raise(). Two associated predicates are associated:
::canReduce() and ::mustRaise().
Note: No two adjacent segments can be reduced at the same time.
* Bug: In Katabatic, in GCellTopology, add a new method ::doRp_AccessPad()
to connect to the pads. Create wiring, fixed and non managed by
Katabatic, to connect the pad connector layer to the lowest routing
layers (depth 1 & 2). The former implementation was sometimes leading
to gaps (sheared contact) that *must not* occurs during the building
stage.
Remark: This bug did put under the light the fact that the initial
wiring must be created without gaps. Gaps are closed by making doglegs
on contacts. But this mechanism could only work when the database if
fully initialised (the cache is up to date). Otherwise various problems
arise, in the canonization process for example.
* New: In Katabatic, in AutoContactTerminal::getNativeConstraintBox(),
when anchored on a RoutingPad, now take account the potential rotation
of the Path's transformation. Here again, for the chip's pads.
* New: In Kite, support for reduced AutoSegment. TrackSegment associateds
to reduced AutoSegment are *not* inserted into track to become
effectively invisibles. When a segment becomes reduced, a TrackEvent
is generated to remove it. Conversely when it is raised a RoutingEvent
is created/rescheduled to insert it. All this is mostly managed inside
the Session::revalidate() method.
* New: In Kite, in KiteEngine::createGlobalGraph(), in case of a chip,
mark all global routing vertexes (Knik) that are under a pad, as blockeds.
* Bug: In Cumulus, in PadsCorona.Side.getAxis(), inversion between X and
Y coordinate of the chip size. Did not show until a non-square chip
was routed (i.e. our MIPS R3000).
* Change: In Stratus1, in st_placement.py add the ClockBuffer class for
backward compatibility with the MIPS32 bench. Have to review this
functionnality coming from the deprecated placeAndroute.py.
In st_instance.py, no longer creates the Plug ring of a Net.
In my opinion it just clutter the display until the P&R is called.
Can re-enable later as an option (in Unicorn).
* Change: In Unicorn, in cgt.py, more reliable way of loading then running
user supplied scripts. Borrowed from alliance-checker-toolkit doChip.py .
* Change: In KiteEngine::wipeoutRouting(), remove only the Contacts
that are *not* anchored. Any other will be indirectly destroyed.
* New: In GraphicKiteEngine, add an encapsulation and a menu for
wipeoutRouting().
* New: In Hurricane, in Cell, no longer create rings of RoutingPads when
flattening the nets. Put that functionnality into a separate method
::createRoutingPadRings().
This allow to perform the Net flattening in Etesian *without*
the rings, which slow it down. Then the rings are created by
Knik/Kite. This also solves the double ring creation when doing
P&R of a complete chip (rings where created twice: in the core
block for Etesian and at chip level for Kite).
* Change: In Etesian, slight beautification of the printed informations.
(psychorigid me)
* New: In Hurricane, dedicated class BaseFlags to wrap a set of flags.
Similar to the Mask class, only with a slightly different semantic.
Encapsulation of <unsigned int>.
Also provide support for the Inspector, to have a human-readable
display of the flags.
* Change: In Hurricane, in Cell, regroup all the flags under a Flags
sub-class of Cell. No more mixing between booleans and bit flags.
(first use of BaseClass).
* In Hurricane, CRL Core & Knik, many small corrections to suppress
annoying warning messages at compile time.
Most noticeably, Bison errors in VstParserGrammar generated by
rules and token with mismatched return value type. This was not
problematic because the badly defined return value where not used.
But still...
* Bug: In CRL Core, in VectorPortMap::VhdlPortMap(), if the connection
was made to *non-contiguous* bits of an otherwise *contiguous* vector,
it was using a span instead of the separate bits. Now check that
bits are contiguous (delta: +1/-1) and the delta do not change of
sign.
* Change: In Etesian & Kite, the Python interface function ::setViewer()
was checking that the argument was indeed a CellViewer, but in text
mode it is None. Now, silently ignore the argument if it cannot be
converted into CellViewer.
* New: In Hurricane, in Collection add simple STL iterator support.
So now the C++11 "for" instruction can be used instead of the
in-house "forEach".
Example:
forEach ( Component*, icomponent, net->getComponents() ) {
cout << (*icomponent) << endl;
}
Become:
for ( Component icomponent : net->getComponents() ) {
cout << icomponent << endl;
}
* New: In Kite, in BuildPowerRails more accurate GCell density computation
under the pad area, to limit the overloaded messages.
* New: In Cumulus, In BlockCorona, remove the vertical METAL3 blockages
and replace them by horizontal blockages completly enclosing the
corona big vias in all layers. This way the I/O wires that goes
through the corona are guided to be straight and do not creates
unsolvable doglegs due to the presence of big vias.
* Change: In Kite & Etesian, small typo: refactor the method
"::wipeOutRouting()" into "::wipeoutRouting()" (indulge me, I'm a
code maniac).
* Bug: In Hurricane, in PyHurricane.h the macro HCATCH was not catching
standard STL exceptions. This was the source of the cryptic message:
"Fatal Python error: Py_EndInterpreter: thread still has a frame"
The Python interpreter was interrupted uncleanly bypassing it's own
exceptions mechanism.
In PyViewer, the Viewer *do not* inherit from a base class (in the
Python export).
* New: In Hurricane, in DbU, compute maximum values (in double) for
grid, lambda & physical (in meter) so now the DbU::toGrid(),
DbU::toLambda() & DbU::toPhysical() methods can check for out of
bound values, and throw an exception.
* Change: In Hurricane, ExceptionWidget::catchAllWrapper() now returns
a boolean, set to <true> if an exception has been catched. Allow
callers to interrupt themselves if a problem has occured.
* Bug: In Kite & Etesian, in the Python wrapper, send a Python exception
if catchAllwrapper() did return true, instead of continuing...
* Change: In Kite & Etesian, adds a setViewer() method (exported in Python)
to use the graphical ExceptionWidget when in graphic mode.
* Bug: In Cumulus, in PadsCorona.py the check for the core vs. chip size
was not returning False when invalid.
* New: In CRL Core, in Vst driver, add a support IEEE VHDL. Inactive for
now as I don't see clearly the policy for selecting it or not.
Remove the code of the old Vst driver.
In Blif parser, check for non-existent models (incomplete or
corrupted Blif file). Found by G. Gouvine.
* New: Added extras file for IDE-like support under Emacs.
* New: In CRL Core, created a LibraryManager widget. It provides a
composite information based on what is present, for each
Alliance library:
1. - A Cell in memory, without Catalog::State.
2. - A Catalog::State, with or whithout the Cell in memory.
3. - The files of the Cell in the librariy's directory.
4. - A file with a format referenced for one of the importers.
File type recognition is based *only* on the file extension,
so it may easily confused. Be careful about what you put in
the library's directory.
One of the big limitation is that it will not display Hurricane
libraries that do not have the AllianceLibrary extension.
This widget is put in a separate library <libmanager>, included
in the default CRLCORE_LIBRARIES.
* Change: In CRL Core, in State (through the loader), now sets the
InMemory flag (event if nobody uses it yet...). Display it in
the state _getString().
In AllianceFramework, new getAllianceLibraries() method.
In CatalogExtension, make the static method "get()" publicly
accessible, for sometimes we want the whole State.
* Bug: In vlsisapd, in Path, the pathcache was not rebuild when it
should, leading to incorrect results.
* New: In vlsisapd, in Path, added a listdir() method to access the
contents of a directory and a stat() method to poll the status
of a file/directory.
Rename the ".string()" method in ".toString()" to avoid
tricky name resolution with std::string, refactor in all the
other tools.
* Change: In Hurricane, in Controller, no longer oversize the fonts
of the table's headers.
* New: In Unicorn, in UnicornGui, integrate LibraryManager.
* New: In Hurricane, In NetAlias & Net, add an AliasList collection to
iterate over all the aliases names (this *not* include the main
net name).
* New: In Hurricane, In Cell, Instance & Net add support for cloning and
uniquification (update documentation).
All Cells that are uniquified from a given model are kept in an
Uniquify relation. This relation allows to get all the clones and
generate unique clone names by adding a "_uXX" suffix.
* Bug: In Hurricane, the Cell::_isFlattenLeaf attribute was not initialized
in the constructor.
* Change: In CRL Core, in AllianceFramework::getCell(), no longer destroy
a partially loaded Cell in case of parser failure, let the incomplete
Cell be.
* New: In CRL Core, in ApParser, if all the instances are placed, sets the
Cell::Placed flag.
* Change: In CRL Core, in BlifParser, complete rewrite of the parser.
Not so good an idea afterwards...
* New: In Etesian, uniquify the design before placing.
* Change: In Kite, display the list of unrouted wired after all other
statistics.
* New: In Hurricane, In Cell, add Placed and Routed flags to know the
state of the Cell.
* Change: In CRL Core, In ApDriver, do not save the RoutingPads as
external connectors if the design is *not* routed (create
conflics on reload with the newly generated RoutingPads).
* Change: In Etesian, set the Placed flag on the Cell.
* Change: In Kite, set the Routed flag on the Cell.
* Change: In Cumulus, in RSavePluginAll, save the layout only if it
has a bounding box.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
Use a structure based on a simple ring of NetAliasHook. The Net
holds a global map, sorted by names of all the aliases of all Nets.
Elements NetAliasesHook of the map are slaves of ring whose master
is an attribute of the Net (it is *not* in the map, as the primary
name of the Net).
In case of merge, the aliases of both Nets are merged and the
name of the merged one become an alias.
The Cell::getNet() looks in both the Net map and the aliases to
find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
configuration files so the real technology is read as early as
possible to set up the <gridsPerLambda> factor before any lambda
is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
a design into VHDL compliant names (mainly from Blif/Verilog).
This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
messages. Align the loading progress information on the other
parsers.
Add a capability to select which component of the design will
be returned, if there are more than one. Use the "." as separator.
For exemple you can request "Processor.Alu", which will load
the "Alu" component from the design in "Processor.blif".
To be able to save a Blif loaded design, systematically convert
all the name for VHDL compliance, as it is the format used by
the Coriolis native files (vst).
Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
Partly redundant with the previous one. Have to better organize
that later.
* Bug: In Hurricane, In CellViewer, pass by a temporary pixmap when
shitfing right (and bottom). We were already using the AutoCopy
buffer for the opposites moves... Seems that the drawPixmap()
may have changed of implementation.
Explanation of the diagonal lines, see QTBUG-31579 that affect
Qt 4.8.5. Temporary work around, force the pen to have a width
of 2 pixels (for _normalPen & _linePen).
* Change: In Hurricane, in CellViewer remove the redraw by whole
strip mechanism (offsetVA).
* New: In Hurricane, In CellViewer::DrawingPLanes add a tracking of
the brush offset to avoid small irregularities at the border of
two separately drawed areas.
* Bug: In Hurricane, in Graphics, display a warning about the
diagonal lines when using Qt 4.8.5.
* New: In VLSISAPD, in Configuration, add a new priority level UserFile
to distinguish between the system configuration files and the user's
configuration files (which take precedence).
* New: In Hurricane, in Script (Python), improve the API to be able
to support Chams (and remove the duplicate capability from it).
Add separate functions to perform the initialize/run(s)/finalize
cycle step by step.
* Change: In CRL Core, rename real technology <hcmos9> to <hcmos9gp>,
it's offcial name from CMP/ST. This is the 130nm.
Move the reading of the symbolic & real technologies names from
coriolisInit.py to helpers.__init__.py, to be shared with
chamsInit.py.
To avoid a clash of names inside of helpers, the two variables
of techno.py are renamed "symbolicTechnology" and "realTechnology".
Move python init system from crlcore/src/crlcore to crlcore/python.
* New: In CRL Core, In Utilities, add site-packages/pharos to the
PYTHONPATH.
* Change: In Kite, move python init system from kite/src/init to
kite/python.
* Change: In Cumulus, in Configuration.py, in the horizontal & vertical
wire creation adds new flags ExpandWidth to draw wires one lambda
bigger than the minimal width (see ClockTree.py patch).
* Change: In Cumulus, In ClockTree.py, use non default width to draw
wires of the H branch of the clock tree. This is to prevent them
to be recognized as "manual global routing", which they are not
and not event topologically compatible.
* Bug: In Kite, in BuildPowerRails, change the way clocks are detected
when working on a single block (not a whole chip). Now look only
in clock which are external and do not filter out already routed
ones.
* Change: In KiteEngine, in createGlobalGraph(), systematically call
flattenNets() so nets that are added after the first flattening
in the placer are also flattened. The flattenNets() Cell method
takes care of not flattening twice a net.
* New: In Bootstrap, in ccb.py, check if cmake is installed and issue
a warning, if not.
* New: In Hurricane, added Cell::getDeepNet() to search for a deepnet
given a path and a leaf net. This method is slow and must not be
used too often. Introduced for Kite::BuildPowerRails().
* Change: In CRL Core, in cmos/alliance.conf, modify the clock name
pattern to match the sub-clock signals in the datapath operators.
* Bug: In Etesian, do not blindly reset the top cell abutment-box.
Do it only if it's empty, otherwise keep it.
* Bug: In Kite, in buildPowerRails(), in getRootNet() the management
of clock nets was incomplete. The case of unrouted clock nets
that where not connected to the top core clock net, like the
one in the datapath registers was faulty. They were partly
recognized as unrouteds and partly as blockage generating a
routing deadlock: routage impossible due to blockage generated
from itself...
* New: In Stratus1, add a buildModel() utility function to automate
the model generation and allow a call by the model name (string).
* Change: In Unicorn, in cgt.py, display the Alliance environement.
* New: In Hurricane, in DebugSession, add a new method to activate the
trace inconditionally with a certain level.
* New: In Hurricane, in HyperNet, allow copy construction as there is
no reason to disallow it and we need it now.
* New: In Hurricane, in Cell::flattenNets(), add a new option to prevent
the flattening of the clock net(s). For more safety perform the
DeepNet creation *outside* the Collection loop.
* Bug: In Hurricane, in Cell_HyperNetRootNetOccurrences, skip the
DeepNets because they are the result of another flattening operation.
* New: In Isobar, in PyBasicLayer, export C++ method getBlockageLayer().
* New: In Isobar, in PyRoutingGauge, export C++ method getLayerPitch(),
needed by Cumulus plugins.
* New: In Etesian, EtesianEngine::findYSpin() to look for the Y orientation
if some cells are already placed. Typically the buffers of a clock
tree.
Pass the correct orienation to row_compatible_orientation().
Do not try to add feeds in the ISPD05 benchmarks. For now the
benchmarks are detected through their names (unreliable).
* Change: In Knik, in KnikEngine::initGlobalRouting(), allow the clock
to be routed as an ordinary signal when the clock tree is not
used.
* New: In Kite, in BuildPowerRails, management & detection for the
pre-routed clock.
In KiteEngine constructor, early initialization of the blockage
net to avoid later troubles in BuildPowerRails.
* New: In Cumulus, in ChipPlugin, add support for Etesian plus new
configuration parameter 'clockTree.placerEngine' to select between
Mauka and Etesian.
* New: In Cumulus, in BlockCorona, add blockages in the vertical sides
in the vertical layer to prevent the router to use the vertical
tracks in under the prower lines (for example, blockage in M3
with power line M5).
In Cumulus, in ChipConf add attribute to access the blockage net.
* New: In Cumulus, when the clock tree is disabled, do not generate
the last rail around the block (the clock rail).
* Bug: In Cumulus, in ChipConf use the clock pad to guess the clock
signals and *not* the power pad.
Add more meaningful error messages if a pad global signal is
not found (implicit connexion by name).
* Bug: In Cumulus, in ClockTree, compute correctly the cells Y spin,
that is *from the bottom of the cell AB* (not from 'zero').
* New: In Bootstrap, in Builder & coriolisEnv.py support for RHEL7/SL7.
The sub-directory name is 'el7_64'.
In qt_setup() add QtSvg to list of Qt5 & Qt4 used libraries.
* New: In Hurricane, In Cell add a placeholder for flags. First use to
store whether the Nets have been transhierarchically flatteneds.
* New: In Hurricane, In NetRoutingState add an Unconnected flag for
more accurate diagnosis.
* New: Hurricane, in CellViewer add an entry menu for stress tests.
The script must be named "stressScript.py" in the cwd.
* Change: In CRL Core, in display.conf add a scaling parameter for the
display threhold of the layer. This way we can adapt to different
standard cells height.
* Change: In CRL Core, in ISPD05 bookshelf loader, use the pitch of the
cell gauge instead of a hard-wired 5.0.
* Change: In Cumulus, in ClockTreePlugin, add support for Etesian placer
and a new configuration parameter to choose between Mauka/Etesian.
* New: In Etesian, support for the latest Coloquinte.
Add feed insertion stage.
* Bug: In Kite, In BuildPowerRails, check that _ck is not NULL before
tring to access it's name...
* Change: In Kite, check if the Cell has it's Nets flattened before
doing it (or not).
* New: In Bootstrap, added support for RHEL7 in ccb.py & coriolisEnv.py.
In coriolisEnv.py, under RHEL6, directly launch a shell under
devtoolset-2 (do not put it in .bashrc).
* Change: All tools, compliance with Clang 3.2.
- Call using namespace std *after* at least one include of std has
been used.
- In Utilities.h define both const and non-cont overload for operator<<
of mstream (this was the true cause of the Banner display problem).
- No longer use defaults arguments in templates, instead create two
separated overloads.
- Put template static attributes allocation outside of namespaces
(this one I'm not sure how to justify).
- Protect by NDEBUG variables that are only needed in assert().
- In PyInterval getUnion() & getIntersection() we where silently
overwriting the "self" object (interval).
- In Mauka, *do no* overload _postCreate() and add an argument, breaks
the virtual function mechanism. Rename it into _maukaPostCreate().
Idem for SubRow().
- In Katabatic::GCell(), invalidate() overload a Go funtion but is
used for different purpose at this level. Rename it invalidateCt()
(invalidate *ConTents*).
- Miscellaneous small cleanup.
* Bug: In Kite, in KiteEngine::BuildPreRouteds(), Pin (sub-class of
Contact) must not be considered as a component triggering the
*already routed* state.
* Bug: In Kite, in BuildPreRouteds (GlobalNetTable), when de design
is *not* a full chip, do not try to compare net with _vdde/_vsse.
* Bug: In Kite, in TrackSegment::_postDogleg() when called through
TrackSegment::moveUp(), if no dogleg are created, that is the
segment is "pivoted up" (for example a M3 connected to only
M4 that is pivoted to M5), the segment was *not* rescheduled as
it ough to be. The end result was a M5 in a M3 track...
* Change: In Kite, in Track::checkOverlaps() in case of further
problems, also check that TrackSegments and Track are in the
same layer.
* Change: In CRL Core, in coriolisInit.py now read the configuration
files from a ".coriolis2/" directory. This is to avoid too many
dot files in the user's directory. Files have also been renamed:
.coriolis2.conf ==> .coriolis2/settings.conf
.coriolis2_techno.conf ==> .coriolis2/techno.conf
* Change: In Kite, in kiteInit.py follow the same policy as CRL Core
for configuration file.
.coriolis2.kite.py ==> .coriolis2/kite.py
* Change: In Hurricane, the NetRoutingProperty is moved into Hurricane
from Katabatic. Needed for Knik to be able to access thoses
informations.
* Change: In Hurricane, in RoutingPad::setOnBestComponent(), now in
case of identical area, select the component of lowest id.
This should not be needed if the component ordering was fully
deterministic as it should be (will investigate later).
This is to ensure that the choosen component is always the
same, especially between save/load of a global routing.
* Bug: In Katabatic, in AutoContactHTee::updateTopology(), invalidate
the segments only if the topology is valid (no NULL in the
cached segments).
* Bug: In Katabatic, in GCellTopology::construct(), throw an error
if the topology is bad instead of trying to continue (and core
dump later... ).
* Bug: In Kite, in BuildPowerRails, distinguish the name of the master
net in the pad (for vddi, vssi, vdde, vsse, ck, cki & cko) and the
name of the net in the *chip* netlist. Must use the later to make
comparison as they may differs.
* Change: In Knik, in save/load solution, exclude nets that are not
globally routed by Knik. That is which NetRoutingProperty is not
*Automatic*.
* Bug: In Cumulus, in chip.BlockPower take account of the layer
width extention to sligthy shrink the connector thus avoiding a
notch with standart cell in some cases.
* Change: In Cumulus, in chip.ClockTree disable the use of fixed Steiner
trees for the leaf clocks, as it seems overconstrained for the
router. First move was to lower them in M2/M3 (instead of M3/M4)
but that was not sufficent.
* New: In Cumulus, RSavePlugin for recursively saving a physical
hierarchy.
* New: In documentation, first embryo for RDS file. Should have been
in Alliance git, but I prefer to keep newest doc in Coriolis.
* Bug: In Katabatic, in AutoContactTurn::cacheAttach() unset the
"cache invalidated" flag *only* if the h1 & v1 component are
sets. This is needed because we can attach *before* the first
cache revalidation (in the initial building stage).
* Bug: In Katabatic, in AutoSegment::getPPitch() out of bound access
of the top of the RoutingGauge, in case of a top layer segment
with a spin top flag (maybe this shouldn't happen?).
* Change: In Kite, in SegmentFsm::conflictSolveByPlaceds() take
account as conflicting other global, global, blockage *and*
now fixeds.
* Change: In Cumulus, in px2mpx.py more accurate way of transforming
the pad blockages.
* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
variable to define the pad model name extension ("px" for "sxlib
and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
of used for power & clock supply. We may remove the extention in
the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
longer place the accessing contact *at the center* of the
RoutingPad. It works under sxlib because buffers & registers all
have same size terminals. But this is not true under vsxlib,
leading to misaligned contacts & wires. Now systematically place
on the slice midlle track (maybe with one pitch above or below).
This is still very weak as we do not check if the terminal
reach were the contact is being put. Has to be strenthened in
the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
of PyInt for DbU conversions. In PyHurricane argument converter,
automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
in case of discrepency in global net connections (i.e. no net
of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
model name to find "pck_" or "pvddeck_", do not compare the
extension part. But we still use hard-coded stem pad names,
maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
RoutingPads of fixed nets, they are already through the
BuildPowerRails stage (and it's causing scary overlap warning
messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
deep-plug when the core is flat (not sub-modules). All the new
nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
that the core is aligned on the GCell grid (i.e. the slice
grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
while looking for the bigger N-E RoutingPad. Forgot to decrement
the index...
* Change: In Hurricane, in Plug::setNet(), more informative error messages.
* Change: In Hurricane, In Segment, more informative error messages.
* Change: In Hurricane, In DeepNet, accessor for the Net occurrence.
* Bug: In Katabatic, in AutoSegment::create(), error message uses correct
variables (vertical was using horizontal)...
* Change: In Kite, in BuildPowerRails, already existing wiring in instances
is copied up as blockage. Uses blockage layer instead of true layer
(it was a bug).
* Change: In Kite, in BuildPreRouted, consider as manual global routing
nets with only default wiring (default size wire & contacts).
Non-default routing is flagged as fixed (with the NetRoutingState
property).
* Change: In bootstrap, in ccb, builder and coriolisEnv.py, correct detection
of the windows architecture (32 or 64 bits). Under Cygwin, add the
directory of the dll into the PATH also. Uses "site-package" as the
location of Python modules (*not* "dist-package").
Use gnu++0x under Cygwin instead of c++11.
* Change: In Etesian, if Coloquinte is not found, do not stop the compilation,
just disable the tool altogether.
* Change: In Hurricane, In Backtrace, disable backtrace under Cygwin as it
uses features specific of the glibc.
* Change: In Knik, use HUGE_VAL instead of HUGE (not present under Cygwin),
add the <cmath> header.
* Change: In Unicorn, Coloquinte no longer stops the compilation.
* Change: In bootstrap, in ccb & builder, build by default with Qt4 and
provide a --qt5 command line switch to enable Qt5.
FindBootstrap.cmake now provides a qtX_wrap_cpp() macros to be
independant of the version of Qt being used.
Add all thoses options to the graphical interface to the builder.
* Change: In all the tools using Qt, switch to the qtX_*() macros from
FindBootstrap.cmake.
* Change: In Hurricane, in CellViewer, revert to the Qt4 way of connecting
signal/slots for backward compatibility.
* New: In all to CMakeLists.txt, disable the warning about deprecated
WIN32 under cygwin.
* New: In boostrap, in ccb.py, coriolisEnv.py and builder/Configuration.py
add recognition in uname for the values returned under Windows/Cygwin.
* New: In Documenation, in UsersGuide.rst add some informations about
Cygwin and a section for the devel branch.
Jean-Paul Chaput
Gabriel Gouvine