* New: In CRL::NamingScheme, add a flag VstNoLowerCase, and its
management it in the Verilog to VHDL converter.
* Change: In CRL::BlifParser::Model::toVhdlModels(), disable the
lowercasing of identifiers. We shouldn't apply Alliance VHDL
subset constraits when reading blif files. So we will see
uppercase identifiers in Coriolis.
* Change: In CRL::VstParser, no longer lowercase identifiers that
are *not* VHDL keywords. Uppercases are legals in VHDL...
* New: In CRL::Catalog::State, add a new flag VstNoLowerCase to
tell if the VST driver should keep the uppercases.
* Change: In CRL::VhdlEntity, add a VstNolowerCase flag to disable
the lowercasing.
* Change: In CRL::vstDriver, lower case the file name if needed.
remove the previously opened filename if it differs from the
lowercased one.
* Change: In UnicornGui CTOR, disable VHDL enforcement for the
Blif parser.
* In cumulus.plugins.matrixplacer.py, BETA plugins for getting back
matrix-like netlists placement. This plugin is configured *ONLY*
for Libre-SOC FU-FU matrix 30x30.
* Change: In CRL::BlifParser, formerly, a zero/one cell was added for
each vss/vdd direct connection, generating a huge flock of cells.
Now only generate one per netlist.
It can be discussed whether to old behavior is more desirable,
it is a compromise between wire and area.
* Change: In CRL::AllianceFramework::getCell(), if the Cell is marked
as TerminalNetlist, then it may be a standard cell. So it's layout
must be loaded. So now, systematically try to load the layout of
netlist terminal cells.
* Bug: In karakaze/AnalogDesign.readParameters(), when asserting the
type of dspec[0], it can either be a type (for analog devices) or
a Cell object (*not* a type). So the issubclass may fails.
Now check first if dspec[0] is an *instance* of Cell.
This is an anisotropy in the type of the first element of
the devicesSpecs table, but suppress one superfluous parameter.
* New: In Analog, new Parameter derived class "StringParameter",
to support strings. Also added to the Python interface.
* New: In Analog::Transistor, added StringParameters for specifying
track positions. They are named "G.t", "S.t", "D.t" and "B.t".
* New: In Oroshi/wip_transistor.py, now read the track positionning
devices parameters.
* New: In Karakaze/AnalogDesign.doDevice(), read an optional 14th
parameter holding the track positions (example in ADC-SAR).
* Bug: In Anabatic::AutoHorizontal & AutoVertical, in getGCells()
method, do not display the "NULL GCell under" error message if the
segment has just been created. It could on a "wrong" axis position
so the line probing method may fail.
* Bug: In AnabaticEngine CTOR, if the "blockagenet" is created there,
do not forget to set it's type to BLOCKAGE (to avoid later warnings).
* Bug: In Anabatic::NetBuilder::_load(), do not display a warning if the
blockage net has no RoutingPads (it *must* not have one).
* Change: In Karakaze/analogdesign/AnalogDesign.readParameters(),
only Transistor and Capacitors where manageds. So when a devices in
the dspec was from another type, it did issue an error.
Now cleanly skip unsupported (yet) devices.
* Bug: In Bora::SlicingNode::clearGlobalRouting(), as we are unrouting the
cell, the flags set up by Katana must be reset. The Cell is no longer
"Terminal" and it's nets are "Un-flattened".
* Bug: In Anabatic::Session::_revalidateTopology(), when iterating over
_segmentInvalidateds, the vector can be modified. If it leads to a
reallocation we end up on invalid iterators (using freed memory so
sometimes with overwritten contents). Now, iterate with an index
which warranty that we get a valid item at each iteration of the
loop. And, of course, the vector is ensured to not shrink...
* Change: In Anabatic::Session::Session(), reserve (pre-allocate) at least
1024 elements for all vectors. Mostly prevent the above bug and
avoid constant reallocation.
* Change: In CRL::LefParser::_macroCbk(), create a Catalog entry for the
newly read MACRO (that is Cell) and sets the Logical, Physical,
InMemory and TerminalNetlist flags.
* Bug: In CRL::LefParser::_siteCbk(), check for NULL cell gauge.
* New: In CRL::AllianceFramework, add setCellGauge(), to set the default
cell gauge. Exported to Python.
* Change: In CRL/etc/common/technology.py, create variables for VIA
layers, so we can modify their properties afterwards.
* New: In CRL/etc/node45/freepdk45, port the configuration files to the
new Python "importable" format.
Note: in kite.py, all the gauges (Routing & Cells) must be named
"LEF.CoreSite" to please my LEF parser, so it can match the gauge
name with the SITE name for standard cells.
* Bug: In Anabatic::NetBuilderVH::_do_2G(), forgotten to be reimplemented
from the base class. Simply redirect to _do_xG().
* Change: In Katana::PowerRailsPlanes::PowerRailsplanes(), create plane
from the layers in the RoutingGauge and their associated blockages
instead of sweeping through all the basic layers.
Allow to distinguish bewteen "METAL" (symbolic) and "metal" (real).
* Bug: In Katana::NegociateWindow::createTrackSegment(), *fixed* AutoSegment
in conflict with blockage where removeds. This was creating "holes"
in the Anabatic articulated segment structure. Now just *don't*
create the TrackSegment. Pass the regression tests, but not sure
it is not generating problems elsewhere.
* New: AnabaticEngine::checkPlacement() to issue more clear errors about
a defective placement.
* Bug: In CRL::ApParser::_parseInstance(), the instance coordinates where
stored in *static* variables (boo). Making the parser *not* reentrant.
But in _parseInstance(), it can be recursively called through
getCell() when an sub-instance layout was missing.
Also make non-static all other variables in the various parser
function.
* New: In Anabatic::NetBuilderHV(), added configurations to manage
one Pin M3 + one M1 terminal plus 2 & 3 globals:
* _do_2G_1M1_1PinM3()
* _do_3G_1M1_1PinM3()
They were occuring for the first time in soclayout/experiment7
in the "flat" approach.
* New: In Katana::runNegociate(), mark the newly routed netlist as
"NetlistTerminal" so it is not placed and routed *again* when
reused as an instance (mostly interract with Etesian).
* Bug: In CRL::VstParserGrammar & VstParserScanner, when loading the
instances models, we where loading both logical & physical views.
This was causing cases of reentrency of the parser, with reset
of the lexer static dictionary, leading to memory corruption.
Now the identifiers are stored in the YaccState of each
parsed cell and we only recursively call for the logical view.
* Change: In CRL::ApParser::_parseInstance(), recursively load the
physical views as they are no longer loaded by the Vst parser.
* Change: In CRL::AllianceFramework::getCell(), sets the
TerminalNetlist flag from the state (mode 'C' in CATAL) onto
the cell.
* Change: In EtesianEngine::loadLeafcelllayouts(), new functions to
load the layouts of the leaf cells if only the netlist has been
loaded.
* Bug: In CRL::ApDriver::DumpSegments(), reset the direction field to
NULL between iterations so it is recomputed for each component and
not keeping the first one ever guessed.
* Bug: In Katana::AutoSegment::_preDestroy(), remove the segment from
the source & target AutoContact cache.
In LibreSOC/experiment7, weird placement caused fixed AutoSegment
overlaping blockage to be deleteds. It seems to have never occured
before (or at least, no ended up in core dump).
* Bug: In Hurricane::NetRoutingState::getSymValue(), outrageously bad
computation of the symmetric coordinate when the value was superior
to the axis... (shame on me).
* Change: In Anabatic::Disjkstra::load(), for symmetrically paired nets,
check that the axis of symmetry is *outside* the searchArea.
Otherwise, the two mirrored areas overlaps and the two nets will
unescapably be on top of each other. Issue a warning but still
continue.
* Change: In Anabatic::Vertex::isRestricted(), allow perpandicular
wire to go through struts or thin (less than one routing pitch)
node. May have to recheck in the future and restrict to struts
only.
* Bug: In Bora::HVSlicingNode::updateSymNetAxis(), rescursive call in
child node was not systematically done (bad curly brace position).
Also checks that symmetries are not empty before accessing the
front element (one less core dump).
* Bug: In Bora/SlicingDataModel, the division was done with integers,
leading so there was a rounding *before* we casted to double.
Now, use the BoxSet::getRatio() method and cast to double *before*
dividing.
* Change: In CRL/helpers, cumulus/plugins, oroshi & karakaze,
Move towards more Python PEP8 compliance:
* All indentations sets to 4 spaces (in progress).
* In plugins, remove messages about software collections
and RHEL (too many case could wrongly lead to that).
Instead systematically uses "helpers.io.catch()".
* Put in lowercases all modules names. Note that C++ exported
modules *keep* their Capitalized names (to preserve the
identity with the C++ namespace).
* When making import, use full path.
* Rename the run function from "ScriptMain()" to "scriptMain()".
* Cleanup: In CRL/etc, remove obsoleted configuration files,
the one ending in ".conf". Keep those who have not been ported
to the new style yet.
* New: In Hurricane/src/configuration, first trial at replacing the
C preprocessor macros by C++ templates. Applied first to configuration
from VLSISAPD.
This is unfinished business, just a limited demonstrator for now.
It is installed as a separate Python library "Cfg2" which do not
interact with the rest of Coriiolis.
The end goal is to fully remove boost and merge VLSISAPD useful
components directly inside Hurricane.
* New: In Isobar::PyResistor, manage type RPOLYH and RPOLY2PH.
* Change: In Hurricane::Resistor, rename plate nets from "PIN1" and
"PIN2" into "t1" and "t2" (try to respect uniform naming scheme).
* New: In Karakaze/AnalogDesign.py, support for reading Resistor
parameters.
* New: In Orosshi, ResistorSnake.py imported from Mariam Tlili's work
and associated Resistor.py to make parameter conversion.
Currently we only uses vertical layout for resistors.
Added METAL2 horizontal terminals for resistors.
* Bug: In CRL::ApDriver::DumpSegments(), when saving RoutingPads build
on Pin *not* at the top level (that is, Pin from an instance),
use the pin's orientation to choose the segment type.
* NORTH/SOUTH becomes a Vertical.
* EAST/WEST becomes an Horizontal.
Formerly, the segment direction was guessed only for the bounding
box, leading to segments in incorrect directions leading to DRC
errors (in nmigen/ALU16, net "b(10)").
* Bug: In CRL/symbolic/cmos/technology.py, forgotten import for
WarningMessage.
* Change: In all tools, FindTOOL.cmake, no longer use LIB_SUFFIX to
search for tool libraries but try "lib64/" then "lib/".
* Change: In bootstrap/socInstaller.py, take Debian 10 into account.
* Change: In bootstrap/docker, move from Debian 9 to Debian 10.
* Change: In bootstrap/coriolisEnv.py, no longer rely on the uname to
choose the library directory (lib64 or lib), but instead look for
those locations (lib64 gets precedence).
* Change: In Hurricane::DbU::setGridPerLambdas(), allow the grid per
lambda to be even. Needed when using nsxlib libraries that are
drawn using a "half lambda" (two lambdas to get an Alliance lambda).
* New: In Oroshi/python, integrated capacitors. Modifications and
correction from Mariam's code:
* No need to redefine __setattr__() on CapacitorUnit.
* Pitch horizontally & vertically (symbolic routing tracks) the
devices.
* Put the horizontal access tracks on the routing pitch.
* Sets the horitontal metal2 wires as external components and
NOT the capacitor plates themselves.
* Makes the size (plates) of the unit capacitor a multiple of
the foundry grid, not a floating number...
* Correct the net ownership of horizontal tracks in
drawHRoutingTracks().
* Simplification & put error management directly inside of
__isCapacitorUnitOK__().
* New: In Karakaze/python/AnalogDesign, capacitor spec now include
the dummy parameter.
In the Cell/Instance hierarchy, the "terminal" and "leaf cell" concepts
where not clearly defined and partially overlapping. Now, "Terminal" is
the refer to the physical hierarchy (layout) and "TerminalNetlist" to
the logical hierarchy (netlist). The logical hierarchy can be less deep
than the physical one thanks to a Cell dedicated cell flags. Collections
related to the physical hierarchy keep their old names, the one related
to the logical hierarchy are renamed from "Leaf" to "TerminalNetlist".
The name "Leaf" was too ambiguous (leaf for *what* hierarchy).
* Change: In Hurricane::Device, set the "TerminalNetlist" flag once and
for all. No need set it in all the derived classes again.
* New: In Hurricane::MultiCapacitor, added new parameter "dummy" to
create dummies around the capacity matrix.
* Change: In Hurricane::Cell, remove "Leaf" related methods, replace
them by "TerminalNetlist" one, especially Collections. Now we have
two clear sets of Collections to walkthough the layout or the
netlist.
Change the "Terminal" flag into "TerminalNetlist".
* Change: In Hurricane::CellCollections, rename "Leaf" into
"TerminalNetlist" collections and apply the new semantic to the
locators.
* Change: In Hurricane::DataBase, Leaf to TerminalInstance renaming.
* Change: In Hurricane::DeepNet, Leaf to TerminalInstance renaming.
* Change: In Hurricane::HyperNet, Leaf to TerminalInstance renaming.
* Change: In Hurricane::Instance, Leaf to TerminalInstance renaming.
* Change: In Hurricane::Viewer::HierarchyInformations, Leaf to
TerminalInstance renaming.
* Change: In CRL::AllianceFramework, Leaf to TerminalInstance renaming.
* Change: In CRL::Catalog, Leaf to TerminalInstance renaming.
* Change: In CRL::ApParser, Leaf to TerminalInstance renaming.
* Change: In EtesianEngine::AddFeeds, Leaf to TerminalInstance renaming.
* Bug: In EtesianEngine::resetPlacement, move there the loop over
non terminal netlist instances to flag fully placed sub-blocks
as terminal for the netlist. Only then remove the feed cells
from unplaced instances. Previously, the feed cells where stripped
even from already placed instances.
* Change: In Katana, Leaf to TerminalInstance renaming.
* Bug: In Bora::PyDSlicingNode, allow the range parameter to be the
Python None object when we do not want to pass one but need to
have it as positional parameter.
* Change: In Cumulus/clocktree/ClockTree.py, Leaf to TerminalInstance
renaming.
* New: In Hurricane::Cell::isLeaf(), a leaf cell was defined as one
without instances. Now it can be software defined with the
"FlattenLeaf" state. If it is flagged "flatten leaf" is will be
considered as a leaf by the trans-hierarchical walkthrough.
This flag is also set for Cells in the Alliance CATAL.
* New: In Hurricane::Cell_LeafInstanceOccurrences::progress(), add a
test to prune leaf cells.
* Bug: In Hurricane::getComponentOccurrences(), when calling the
locator constructor, the "withLeafCells" argument was forgotten
and was getting the value of "doExtraction" (wich, fortunately,
was the same).
* Change: In Hurricane::HypreNet_LeafPlugOccurrences::progress(),
prune the leaf cells instead of the terminal ones.
* Change: In Hurricane::HypreNet_ComponentOccurrences::progress(),
prune the leaf cells instead of the terminal ones.
* New: In Hurricane::Cell, add a "useFlattenLeaf" mode to take into
account or ignore the "FlattenLeaf" flag when doing trans-
hierarchical walkthrough.
Not sure if it shouldn't be systematic.
* New: In Etesian::toColoquinte() and other, activate the "FlattenLeaf"
mode for all walkthough. So we can stop at already placed sub-blocks.
* Bug: In Etesian::toColoquinte(), when placed sub-block where present,
the number of instances was under estimated, so the instance array
was oversized and the end went unitialized. So we were getting all
kind of strange behavior from Coloquinte...
Now throw an exception if the number of instances differs from
the computed size.
* Bug: In Etesian::toColoquinte(), as for the instance array, now
correctly compute the size with the ecluded nets (supplies, clocks).
* Bug: In Etesian::resetPlacement(), event if the Cell is unplaced,
go through the instance list to remove the potential feed cells.
The netlist is written back after placement *with* the feed
cells added. So, when loading again, they where cluttering the
netlist and giving feed redefintions warning. They also generated
erratic behaviors.
* New: In Anabatic::NetBuilderHV, added configurations for:
* 1G_1M1_1PinM3
* 1G_xM1_1PinM2
* 2G_xM1_1PinM2
* doRp_AccessNorthPin
* New: In Anabatic::NetBuilderHV, added Pin management in SingleGCell.
* Bug: In Anabatic::NetBuilderHV::_do_xG_1PinM3(), the North/South
global routing configuration was forgotten (only East/West).
* Bug: In Katana::TrackFixedSegment, the blockage net was a static
variable initialized at the first run. So we were getting stuck
with the blockage net of the first cell to be routed. Of course,
it did show only when Katana was run multiple times in the same
process.
* New: In CRL/etc/node600/phenitec, ported configuration of Phenitec 0.6um
Compliant with DataBase reset.
* New: In CRL/python/helpers, added function "unloadUserSettings()" to
unload Python modules prior to a full reset.
Added "resetCoriolis()" to perform full DataBase reset.
* Change: In CRL::AllianceFramework, make it a derived class of DBo so
the destroy() is now provided.
* Bug: In CRL::AllianceFramework::getCell(), do not attempt any load if
the library list is empty. Should never occur except in case of a
botched databse reset.
* New: In CRL::AllianceFramework, new method "saveCATAL()" to write back
the catalog of a library and "saveCells()" to write back the cells.
Note: only cells actually loaded in memory will be write back.
* New: In CRL::Catalog, add method "saveToFile()" to write back the CATAL
of a library.
* Change: In CRL::ParserDriver, replace "const string&" by "string"
(improved string support of the GNU STL).
* Change: In CRL::ParserSlot, use string instead of Name.
* Change: In CRL::ApParser, make _layerInformation an ordinary attribute
instead of a static one. This allow for it's correct resetting
across databas resets.
* Change: In CRL::VstParserGrammar, reinitialize Vst::framework at each
parser call. Needed to support database reset.
* New: In Hurricane::DBo, add an object counter to be sure that when
we perform a reset, no remaining DBo is allocated. This is different
of the object id which is ever increasing.
Note that, at reset, we check against "1" remaining element as at
this point only Database is still allocated.
Add a new "resetId()" method. MUST NEVER BE CALLED except by
DataBase::_preDestroy().
* New: In Hurricane::Database, new clear() method to remove the Cells
of all the libraries in reverse hierarchical depth order.
Make use of the new CellsSort class.
* Change: In Hurricane::DataBase::_preDestroy(), call "clear()" and
DBo::resetId().
* Change: In Hurricane::Breakpoint, change the default callback to be
a static function. So we can restore it later.
* Bug: In Hurricane::Instance::_preDestroy(), there was yet another
loop of deletion over a collection for the shared pathes.
Replace it by the repetitive deletion of the first element.
* Bug: In Hurricane::Net::_preDestroy(), RoutingPads must be destroyed
prior to any other component.
* New: In Hurricane::ColorScale, add a "qtFree()" method for freeing
the Qt Brush, Pen & Color.
* New: In Hurricane::DrawingStyle, add a "qtFree()" method for freeing
the Qt Brush, Pen & Color.
* New: In Hurricane::Graphics, add a "disable()" method to call the
various "qtFree()" of the sub-objects.
* Bug: In CRL/BlifParser::Model::mergeAlias(), when a signal is aliased
toward $true or $false in a Blif file (through a ".name" statement),
it was directly merged to "vdd" (resp. "vss"), and if it is an
external signal, this leads to its removal, potentially making "hole"
in its interface.
Now, create a gate zero or one for each tied up/low signal. This
way the interface is fully kept. At the cost of some supplemental
gates.
* New: In bootsrap/docker:
* install python3/nMigen tool in all environment.
* Add a new image on top of the coriolis one to have a shell
(with X11 connexion to the host system).
* Upgrade Yosys to 0.9.
* Correct integration of allianceInstaller.sh in socInstaller.py.
* Add a chroot mode to socInstaler.py (for Debian 9 chrooted).
* Allow benchs to be run separately.
* New: In bootstrap/docker, paraphernalia to rebuild and check Coriolis
for Debian 9, Ubuntu 18 & SL 7 on pristine systems. Added scripts
to rebuild Alliance as well and perform the alliance-check-toolkit
regression tests.
* Change: Updated installation documentation. Added a section for docker.
* New: In bootstrap/socInstaller.py, partial redesign of group of commands
to better handles all the cases. Added support for docker context,
and added Alliance compilation "alongside" Coriolis (merged install
tree).
* Change: In bootstrap/coriolisEnv.py, when run in a docker container we
no longer can trust the kernel name to guess the OS, as the kernel is
the one of the host and not the docker guest. This was causing problem
for determining the Python site-package directory. Now just check all
possible locations and stop at the first directory found.
* Change: In documentation, now generate the overall documentation using
Pelican instead of Sphinx. This allows to have an unified approach
between the coriolis.lip6.fr website and the local documentation.
So we keep using "only" two doc generators: doxygen & Pelican.
* New: In Karakaze/Oceane.py, now also read capacitor & resistors parameters.
In AnalogDesign.readParameters(), get the capacitor parameters from
Oceane into the "device spec" (dspec). Translate form OSI unit to
Coriolis units (F -> pF).
* Bug: In Bora::NodeSets::create(), Capacitor matrix parameters where never
read due to a misplaced curly brace (at the matrixRange dynamic_cast<>
test).
* Change: In Bora/PyDSlicingNode, now check that the parameter is either
a StepParameterRange or a MatrixParameterRange.
Also add a check that the Instance name exists...
* Bug: In Bora::SlicingPlotWidget::updateSelectedPoint(), as we display
only the transistor parameters in dynamic labels, do not forget to
skip resistor and capacitor. Otherwise we end up in out of bound
access in the vector of labels.
Jean-Paul Chaput
Mariam Tlili
Staf Verhaegen