This non-deterministic behavior was showing only in the ARMv2a benchmark
around event 180k...
* Bug: In Anabatic::Session::_netInvalidateds & _netRevalidateds, the
set<> was still sorted on pointers. As contacts & segments can be
created to maintain connexity after a layer change, we got a
discrepency in objects Ids that may generate a change in ordering
later.
* Bug: In Katana::Session::_doRemovalEvents(), the set of Tracks that
got elements deleted was still using pointers. Now we use a TrackSet
sorted on (direction,depth,axis). This should not have created
a change in the results, as destructions do not change Ids, but it
genereate extra differences in traces.
* Bug: In Anabatic::AutoSegment::reduceDoglegLayer(), we did not check
that not only source and target depth span was zero, but also both
on the same one. This was seen in the RISC-V where a METAL2 small
segment was demoted into METAL1 causing a gap in the routing (and
a short in the underlying standart cell).
* Bug: In cumulus/plugins/PadsCorona.py, when a pad is at the beginning
or at the end of the side, the pad corona terminal may be outside
the corona range (not directly facing it). In that case, create a
bend to reach it.
Worse, in some case more than one (but likely no more), could be
in that case, so not only do we create a bend but also make a
shift in the bended segment so two consecutive ones are not on the
same axis, causing shorts.
If both end pads of a corner are in that case, we cannot prevent
a short, so at least, issue a warning.
* Bug: In CRL::Vhdl, the Entity::VstUseConcat was not passed correctly
along, so we did get a strange mix of conat and direct assignment.
* New: In Unicorn/cgt.py : added --vst-use-concat options to control
the VST driver behavior.
* Bug: In CRL::ApDriver & CRL::ApParser, when saving a fused net, do not
use it's name but put a star (*) character to set it anonymous.
Having all component named was creating problems in cougar and
subsquently in yagle (bad name for master latch).
Conversely, in the parser, if the name of the net is "fused_net",
make it a real fused_net and not an ordinary one.
* New: In CRL::AllianceFramework::saveCell(), through the view flag we
can pass an option 'CRL::Catalog::State::VstUseConcat' to tell the
driver tu use or not the concat '&' in PORT MAP statements.
It is not completely clean that the flag for controlling the VST
driver behavior is put in the Catalog states, but it's easier for
now...
And, of course, exported at Python level.
* New: In CRL/etc/symbolic/phenitec06, configuration for symbolic
layout targeted for Phenitec 0.6um (do not contains any NDA
covered informations). Could be used for any 3 metal layers
techno.
* Bug: In Cumulus/plugins/chip/Configuaration.py, _setStackposition()
disable stack error when there is no slave component on the stack
(happens when the stack consists only of one contact).
* Change: In Cumulus/plugins/chip/PadsCorona, if the external pins of
the corona are in GCells that are also under the core block ring
power lines, they are flagged as "go straight" and this produce
impossible configurations for the router to solve. Now we ensure
that there is one free GCell all around the corona border.
* Bug: In Cumulus/plugins/chip/Configuration.py & PadsCorona.py,
at the begin/end of a side of pad, connectors can be outside the
corona range (i.e. not directly face to face). Now make a dogleg
if needed. This is a work in progress as if there are two of them,
they will short on the perpandicular part. We must compute a
shift.
* Change: In Anabatic::AutoHorizontal::_canSlacken(), if the source or
target contact is in a GCell flagged "go straight", do not slacken,
which would create a dogleg. This case is usually meet under big
power rails that render a dogleg impossible to place as all tracks
are used.
Same modification for AutoVertical.
* Bug: In Cumulus/plugins/core2chip/CoreToChip.py, when creating the ioNet
objects, when a signal is an enable we must not set the external chip
net (the name for the PAD terminal) as it may be set later if it is
also used as an individual pad.
* Change: In Cumulus/plugins/core2chip/CoreToChip.py, in IoNet select
the external I/O net (pad connected) signal to be generated in the
context of the I/O pad instanciation. This should allow an enable
signal in one pad to be also used in a direct output pad.
* In CRL::vstDriver(), remove the Vhdl::EntityExtension right after driving
the file. This avoid keeping in memory a mostly usnused structure and
solve the "second write after modification" problem.
* New: In Cumulus/plugins/CoreToChip, added support for Tristate ouput
pads and bidirectional pads.
Added capability to name the I/O pad instance and their external
terminals so we can override the default naming scheme.
Mandatory anyway for bidirectional and tristate I/O pad as we
cannot guess the core net grouping (in/out/enable).
Support is available for symbolic CMOS and AMS c35b4 (but not
published due to NDA).
* Change: In Cumulus/plugins/chip/Configuration.py, the configuration
file is now named simply "ioring.py" instead of being prefixed by
the design name. As a consequence we can have only one chip per
directory. But now all the tools, for any design in that directory
can peek datas into it.
* Change: In Hurricane::Cell_LeafInstanceOccurrences, add the ability to
walkthrough the leaf of one specific top-level instance.
* Change: In Hurricane::Cell_NonLeafInstanceOccurrences, add the ability to
walkthrough the leaf of one specific top-level instance.
* Change: In Hurricane::Cell:
getLeafInstanceOccurrences() and getNonLeafInstanceOccurrences(), now
have a parameter Instance* to select the leafs we want to walk through.
If set NULL (default value) browse through all the instances,
as before.
* Change: In Hurricane::DeepNet, add forgotten Inspector support.
* New: In EtesianEngine, add a "block" (and Instance) attribute to allow
the placement of one specific bloc. If we want to place the core of
a chip and take into account the external terminals (if they are not
already fixed as Pins at the edge of *said* block). We must place
the core *in the context* of it's instanciation in the corona.
Note for G. Gouvine : Pin & external RP should be taken into account
starting at line 629 of EtesianEngine.cpp...
* New: In cumulus/plugins/chip/Chip.py, make use of the new block
placement feature of ETesian.
* Bug: In KatanaEngine::create(), perform a pre-check to prevent trying to
route whole chip, which is forbidden an leads to annoying core-dumps.
Routing must take place "at most" at Corona level.
* Bug: In KatanaEngine::PowerRails, create a plane for METAL1 blockage.
Not completely sure this was a bug...
* Change: In CRL/BlifParser::Model::mergeAlias(), do not always merge the
net2 with net1 (RHS with LHS of the ".name" instruction). This may
result in a name change in the design interface (external net).
Instead, merge any internal net with the external, so keep the
external net name. If both are external, keep the one with the lower
id (which should have been created first).
* Change: In Hurricane::SharedName, replace the incremental Id by a hash key.
This is to ensure better deterministic properties. Between use cases,
additional strings may have to be allocated, shitfing the ids. Even if
hash can be duplicated, we should be able to ensure that the absolute
order in map table should be preserved. Supplemental strings are inserted
in a way that keep the previous order.
* Change: In CRL/etc/symbolic/cmos/kite.conf, add "katabatic.routingGauge"
default parameter value ("sxlib").
* Change: In CRL/etc/common/technology.conf, define minimal spacing for
symbolic layers too (added for METAL4 only for now).
* Change: In CRL::Histogram, extend support to dynamically sized histograms.
Add a text pretty print with table and pseudo-curve.
* Change: In Cumulus/plugins/ClockTreePlugin, create blockage under the
block corona corners so the global router do not draw wire under them.
This was creating deadlock for the detailed router.
When the abutment has to be computed, directly use Etesian to do it
instead of duplicating the computation in the Python plugin.
* New: In Etesian, as Coloquinte seems reluctant to evenly spread the
standard cells, we trick it by making them bigger during the placement
stage. Furthermore, we do not not uniformely increase the size of the
cells but create a "bloating profile" based on cell size, cell name
or it's density of terminals. Currently only two profiles are defined,
"disabled" which does nothing and "nsxlib" targeted on 4 metal layer
technologies (aka AMS 350nm, c35b4).
* Bug: In Knik::MatrixVertex, load the default routing gauge using the
configuration parameter "katabatic.routingGauge" as the default one
may not be the first registered one.
* New: In AnabaticEngine::setupNetDatas(), build a dynamic historgram of
the nets terminal numbers.
* Bug: In Anabatic::AutoContact::Invalidate(), always invalidate the
contact cache when topology is invalidated. In case of multiple
invalidations, if the first did not invalidate the cache, later one
that may need it where not allowed to do so. The end result was correct
nonetheless, but it did generate annoying error messages.
* Bug: In Anabatic::AutoContactTurn::updateTopology(), bad computation
of the contact's depth when delta == 2.
* Bug: In Anabatic::Gcell::getCapacity(), was always returning the west
edge capacity, even for the westermost GCell, should be the east
edge in that case.
* New: In Anabatic::AutoSegment, introduce a new measure "distance to
terminal". This is the minimal number of segments separating the
current one from the nearest RoutingPad. This replace the previous
"strong terminal" and "weak terminal" flags.
This distance is used by Katana to sort the events, we route the
segments *from* the RoutingPads *outward*. The idea being that if we
cannot event connect to the RoutingPad, there is no points continuing
as thoses segments are the more constraineds. This gives an order close
to the simple ascending metals but with better results.
* New: In Anabatic::AutoSegment, introduce a new flag "Unbreakable", disable
dogleg making on those segments. mainly intended for local segments
directly connecteds to RoutingPads (distance == 0).
* New: In Anabatic::AutoSegment, more aggressive reducing of segments.
Now the only case where a segment cannot be reduced is when it is
one horizontal branch in a HTee or a vertical on a VTee. Check if,
when not accounted the source & target VIAs are still connex, if so,
allow reducing.
* New: In Anabatic::AutoContact, new state flags CntVDogleg & CntHDogleg
mainly to prevent making doglegs twice on a turn contact. This is to
limit over-fragmentation. If one dogleg doesn't solve the problem,
making a second one will make things worse only...
* Bug: In Anabatic::Configuration::selectRpcomponent(), we were choosing
the component with the *smallest* span instead of the *bigger* one.
* New: In Anabatic::GCell, introduce a new flag "GoStraight" to tell that
no turn go be made inside those GCells. Mainly used underneath a block
corona.
* New: In AnabaticEngine::layerAssign(), new GCellRps & RpsInRow to manage
GCells with too many terminals. Slacken at least one RoutingPad access
when there is more than 8 RoutingPad in the GCell (slacken or change
a vertical METAL2 (non-preferred) into a METAL3).
* Change: In Anabatic::NetBuilderHV, allow the use of terminal connection
in non-preferred direction. That is, vertical METAL2 directly connected
to the RoutingPad (then a horizontal METAL2). This alllows for short
dogleg without clutering the METAL3 layer (critical for AMS c35b4).
Done in NetBuilderHV::doRp_Access(), with a new UseNonPref flag.
Perform some other tweaking on METAL1 access topologies, to also
minimize METAL3 use.
* New: In AnabaticEngine::computeNetConstraints(), also compute the
distance to RoutingPad for segments. Set the Unbreakable flag, based
on the distance and segment length (local, short global or long global).
New local function "propagateDistanceFromRp()".
* Change: In AnabaticEngine.h, the sorting class for NetData, SparsityOrder,
is modificated so net with a degree superior to 10 are sorted first,
whatever their sparsity. This is to work in tandem with GlobalRouting.
* New: In Katana::TrackSegmentNonPref, introduce a class to manage segment
in non-preferred routing direction. Mostly intended for small METAL2
vertical directly connected to RoutingPad. Modifications to manage
this new variant all through Katana.
* Change: In Katana::GlobalRoute, DigitalDistance honor the GoStraight flag
of the GCell. Do not make bend inside thoses GCells.
* Change: In KatanaEngine::runGlobalRouter(), high degree nets (>= 10) are
routed first and whitout the global routing estimation. There should be
few of them so they wont create saturations and we want them as straight
as possible. Detour are for long be-points.
Set the saerch halo to one GCell in the initial routing stage (before
ripup).
* Bug: In KatanaEngine & NegociateWindow, call _computeCagedconstraints()
inside NegociateWindow::run(), as segments are inserted into tracks
only at that point so we cannot make the computation earlier.
* Change: In Katana::Manipulator::repackPerpandiculars(), add a flag to
select whether to replace the perpandiculars *after* or *before* the
current segment.
* Change: In Katana::NegociateWindow::NegociateOverlapCost(), when the
segment is fully enclosed inside a global, the longest overlap cost
is set to the shortest global hoverhang (before or after).
When the cost is for a global, set an infinite cost if the overlapping
segment has a RP distance less or equal to 1 (this is an access segment).
* Bug: In Katana::PowerRailsPlane::Rail::doLayout(), correct computation of
the segments extension cap.
* New: In Katana::QueryPowerRails::addToPowerRail(), add support for Pad.
* Change: In Katana/PreProcess::protectCagedTerminals(), apply the contraints
to any turn connected to the first segment of the RoutingPad so the
perpandicular constraints got propagated to the perpandicular segment...
* Change: In RoutingEvent, cache the "distance to RP" value.
* Change: In RoutingEvent::Key::compare(), sort *first* on distance to
RoutingPad, then layer depth. If both distance to RoutingPad is null,
then sort on segment length.
* Change: In RoutingEvent::_processRepair(), try a repack perpandicular with
perpandiculars first (then with perpandicular last, then give up).
* Change: In SegmentFsm::bindToTrack() and moveToTrack(), set an axis hint
when creating the insertion event.
* Change: In SegmentFsm::_slackenStrap(), add a step through slacken between
minimize and maximum slack (wihch directly end up in unimplemented).
* Change: In Session::_addInsertEvent(), add an axis parameter needed when
the axis of the segment is not the one of the track (case of wide
segments or non-preferred direction).
* Bug: In Track::_preDestroy(), bad management of the TrackElement reference
count. Destroy the segment only when reaching zero...
* Bug: In Track::expandFreeIneterval(), forgotten to manage case when there
is a set of overlaping segments at the "end" of the track, the
EndIsTrackMax was not set.
* Change: In TrackCost::Compare, increase the cost when an overlaping
segment is at it's ripup limit. We should try *not* to rip it up if
we can. Add a dedicated flag "AtRipupLimit".
* Change: In TrackElement, add proxies for isUnbreakable(), new function
updateTrackSpan().
* New: In TrackFixedSegment CTOR, when a supply wire of METAL2 or above is
found, make the underlying GCells "GoStraight".
* New: In TrackElement::canDogleg(GCell*), check for already done perpandicular
dogleg on source/target (reject if so).
* New: In CRL/etc/symbolic/cmos45/kite.conf, new gauge "msxlib4" for both
routing and cells. Have only 4 metal layers but with all the same pitches
and width. Differs from the 45nm compliant where pitches double starting
from METAL4.
* New: In CRL/etc/symbolic/cmos45/plugins.conf, adjust default parameters for
the clock tree plugin so they are identical to the one of "cmos" (scaling).
* Change: In CRL/python/helpers/io.py, in catch(), do not set up the script
path here as it is non-informative.
* New: In Isobar::PyCell, export the isRouted() and setRouted() to the
Python interface.
* Bug: In CRL::Entity::parseEntity(), check that the closing parenthesis
is the last character of the net name. Issue a more relevant error
message.
* In Anabatic::NetBuilder::_do_xG() and all other unimplemented methods,
throw an error if called from a derived classes instead of just
issuing a message in the debug stream. Avoid later core dumps...
* In Anabatic::NetBuilderHV, implement the builders for GCells with
one pin. Needed to support chip/corona routing.
* Bug: In Cumulus/plugins/Chip.py, check that coronaCk exists before
using it.
* New: In Cumulus/plugins/PadsCorona/Side._placePad(), when routing
a design with symbolic pads, export the chip external "pad"
connectors to be able to perform a lvx (otherwise cougar do not
create external nets).
In Corona._createCoreWire(), set the minimal gap between the pads
and the corona to 6 pitches. Empirical value to avoid DRC errors
with symbolic pads (pxlib).
When successufully done, mark the Corona cell as routed.
* Bug: In Cumulus/plugins/Core2Chip.IoNet, the regex for vectorizet net
was wrong, it was allowing only one digit in the index.
* Bug: In Cumulus/plugins/Core2Chip.cmos, correct management of
pad & corona clock nets. Correct connexion between vdde/vddi.
* Bug: In Unicorn/cgt.py, forgot to execute scripts when in text mode.
* Change: In Hurricane::Error constructors disable the backtrace generation.
(*very* slow).
* Change: In Hurricane::Library::getHierarchicalname(), more compact
naming. Remove the name of the root library.
* New: In Hurricane::Net, new type "FUSED", for component with no net.
More efficient than having one net for each.
* Change: In CellViewer, BreakpointWidget, use Angry Birds icons.
* Change: In CellWidget::State, use the hierarchical name (cached) as key
to the state. This allow to load two cells with the same name but from
different libraries in the widget history.
* Change: In PyGraphics, export "isEnabled()" and "isHighDpi()" functions.
* Change: In CRL/etc/symbolic/cmos/plugin.conf, and
CRL/etc/common/plugin.conf use the physical dimensions converters.
* Change: In CRL/etc/symbolic/cmos/technology.conf, make the GDS layer
table coherent with the default Alliance cmos.rds.
* New: CRL/python/helpers/io.py, put ErrorMessage new implementation here,
along with a new ErrorWidget written in PyQt4. It seems finally that
PyQt4 can be used alongside Coriolis Qt widgets.
New ErrorMessage.catch() static function to manage all exceptions
in except clauses.
* Change: In CRL/python/helpers/, no longer use ErrorMessage.wrapPrint(),
directly print it.
Rewrite the utilities to display Python stack traces "textStacktrace()"
and "showStacktrace()".
* Change: In CRL::AllianceFramework, shorten the names of the libraries.
* Change: In CRL::ApParser & CRL::ApDriver, more accurate translation between
Alliance connectors (C record) and Hurricane::Pin objects. Pin are no
longer made square but thin and oriented in the connecting direction.
Use the new fused net for unnamed components.
* New: In CRL::GdsParser, implementation of SREF parsing, i.e. instances.
Due to the unordered nature of the GDS stream, instances creation are
delayed until the whole stream has been parsed and only then are they
created.
For the sake of reading back Alliance s2r GDS, we assume that any
TEXT following a boundary is the Net name the boundary (component)
belongs to.
Create abutment box for Cells, computed from the bounding box, so
the Hurricane QuadTree could work properly.
Make use of the fused net for unnamed components.
* New: In Cumulus/plugins/chip, complete rewrite of the I/O pad management.
Now we can mix real (foundry) pads and a symbolic core.
To cleanly support the de-coupling between the real part and the
symbolic one we introduce a new intermediary hierarchical level, the
corona. We have now:
Chip --> Pads + Corona --> Core.
At chip level (and if we are using real pads) the layout is fully
real (excepting the corona).
The Corona contains everything that is symbolic. It has symbolic
wires extending outward the abutment box to make contact with the
real wires coming from the pads.
In the pad ring we can use corners instances (or not), pad spacers
or directly draw wires between connectors ring pads.
Provide two flavors: placement only or full place & route.
WARNING: If routing in a second step, *do not route* the *Chip* but
the *Corona*.
* Change: In Cumulus/plugins/clocktree, give the modified Cell an
additional extension of "_cts" (Clock Tree Synthesis) instead of
"_clocked", to follow the common convention.
* New: In cumulus/plugins/S2R.py, encapsulate call to Alliance S2R and
reload the translated Cell in the editor.
* New: In cumulus/plugins/core2chip, provide an utility to automatically
create a chip from a core. To work this plugins must have a basic
understanding of the pad functionalities which may differs from
foundry to foundry. So a base class CoreToChip is created, then for
each supported pad foundry a derived class is added. Currently we
support AMS c35b4 and Alliance symbolic cmos.
* Bug: In Anabatic::Configuration, read the right configuration parameter
"anabatic.topRoutinglayer" (Katana), and not the one for Katabatic...
* Change: In Unicorn/cgt.py, process the plugins in alphabetical order
to ensure a reproductible ordering of the menus...
* Change: In Hurricane::CellViewer, reorganisation of the to level menus.
Add "Misc." and it's two sub-menus "Beta" and "Obsolete".
* Change: In GraphicKiteEngine::addToMenu(), set Kite in the obsolete menu.
* Change: In GraphicKatanaEngine::addToMenu(), set Katana as the standart
router.
* Bug: In CRL/etc/symbolic/cmos/plugins.conf, rails dimensions are no
longer expressed directly in lambda. Must be created using helper.l().
* Change: In CRL::ApParser, slightly more smart management of Pin width.
Must normalize Pin behavior between Alliance & Hurricane as in
Alliance they have only one dimension.
* Change: In CRL::LefImport, if a net name end with "!", assume it's a
global one. Have to check this naming convention.
* Change: In Anabatic::NetBuilderHV::_do_1G_1PinM3() & _do_1G_1PinM2()
now implemented. Needed for the corona routing support.
* Change: In AnabaticEngine::setupPreRouted(), exclude segments outside
the abutment box.
* Change: In KatanaEngine::PowerRails, remove the I/O pad support as now
we route only inside the Corona. So only one vdd/vss/ck are supported.
* New: In cumulus/plugins/ChipPlugin.py, complete rewrite of the chip
support:
* Uncouple pad I/O ring whith real cells (foundry) from a symbolic
core. A new intermediate level "corona" is introduced to handle
the real/symbolic transition.
* Ability to explicitly setup position of the pads on the chip side
in case of uneven distribution.
* Enable clock tree to be build with 3 metal only (M2 to M4) instead
of (M2 to M5).
* Change: In Etesian::Configuration CTOR, use the gauge from the
configuration parameter "anabatic.routinGauge" instead of the default
one.
* Change: In Anabatic::Configuration CTOR, use the gauge from the
configuration parameter "anabatic.routinGauge" instead of the default
one.
* Bug: In Hurricane python module, forgot to add the Segment type.
* Change: In Isobar/layer.getEnclosure() wrapper check and cast the Layer
argument into BasicLayer.
* Change: In CRL::RoutingGauge::getLayerGauge(Layer*), getLayerType() and
getLayerDirection() no longer check layer identity based on layer
mask instead of just Layer* pointer. To allow a unified call wether
the layer is real or symbolic.
* Change: In CRL::RoutingLayerGauge::getTrackIndex() and getTrackPositon(),
no longer consider negative indexes as invalid and reset them to
zero. The check for out of bound index is now left to Anabatic &
Katana.
* Change: In CRL/RoutingGauge.getRoutingLayer() and getContactLayer(),
more detailed error message.
* Change: In CRL/RoutingLayerGauge.getTrackIndex() and getTrackPosition(),
indexes are now signed long instead of unsigned.
* Bug: In Hurricane::Cell::flattenNets(): Same error again, do not create
components while iterating over the components Collection.
Now RoutingPad of top nets are create outside the loop as they must.
* New: In Hurricane::IntrusiveMap, introduce IntrusiveMapConst which allow
to search with a "const Key&" instead of a "Key", sparing the copy
construction of the Key.
* Change: In Hurricane::Cell::NetMap, use the new kind of map with
"const Name&" key access. This speeds up the Cell::getNet() method
by suppressing one copy construction of a Name, which are costly
after all...
Should review the whole code to use "const Name&" everywhere it
is possible.
* Change: In Hurricane::Entity & Hurricane::DBo, displace the unique
identifier from Entity to DBo (move up to the base class).This
to allow us to build deterministic map of DBo requireds in
UpdateSession (which is built upon a SharedProperty).
WARNING: This break the JSON database exportation support, do not
use it until fixed/rewritten.
* Change: In Hurricane::Layer, add an attribute to know if a layer is
associated to a blockage. Modificate accordingly PyLayer and
BasicLayer.
* Change: In Hurricane::SharedProperty, the set of owners (DBo*) is now
stored in a std::set sorted on the objects Ids, instead of a simple
vector. The linera search time through the std::vector was starting
to show (ISPD05 bigblue1).
* Bug: In Isobar::PyInstance, make full contructor signature (5 arguments)
conform to the C++ one. It was only accepting the four first and
forcing the placement status to be FIXED.
* Bug: In CRL/etc/symbolic/ispd05/kite.conf, update for the new configuration
requirements where all distance must be converted into DbU in the
file itself (use "helpers.l()", "helpers.m()"). Apply to the cell &
routing gauges.
* Bug: In CRL/etc/symbolic/ispd05/technology.conf, update for the new
configuration. "helpers.initTechno()" *must* by called first thing
in this file in order for the Technology to be created.
* New: In CRL::AllianceFramework, add matchCellGauge() &
matchCellgaugeByHeight()
* New: In CRL::CellGauge, add a flag to distinguish gauges meant for
IO Pads and an "isPad()" predicate.
* Change: In CRL::Ispd05Bookshelf, flush the UpdateSession stack every
1000 elements additions. Maybe not necessary now the the UpdateSession
property relies on a std::set instead of a std::vector.
* New: In CRL::LefImport, support for SITE and match/create the appropriate
CellGauge on the fly. Specific support for MACROS that are flagged PAD.
Add a dedicated post-treatment for PAD connectors, extend them toward
the boundary of the nearest abutment box side. Tested only on AMS 350nm
c35b4 for now.
This part is most likely to be tweaked for every kind of real foundry
pad that we may encounter...
* Change: In EtesianEngine::findYSpin(), use the C++ "for" construct to loop
over Collections.
* Change: In Unicorn/cgt.py, register the Python/C++ tutorial support by
default.
* Change: In CRL::DefImport, added callback to read the DEF UNITS statement
and perform a correct length conversion. Previously set to read pseudo
lambdas in hundredth of microns.
Added DefParser::getLefCell() to lookup master cells in the LEF
libraries before looking in the Alliance ones (rooted under "LEF"
library).
* Change: In CRL::LefParser::_pinPostProcess(), when no segment suitable
for terminal connexion is found, add all of them. This is a quick hack
and an a correct policy that match all techno must be implemeneted.
* New: In CRL::pyCRL, add a Python wrapper for DefImport.
* New: In CRL/etc/45/ispd18/ added configuration files for the "real"
technology used by the ISPD18 45nm design benchmarks.
* Bug: In Hurricane::Collection::iterator, the iterator use a locator from
a getLocator() not wrapped inside an auto_pointer like GenericLocator.
So the destructor of the iterator must take care of the deletion.
This was showing more and more as we converted forEach() into the
C++ 11 for syntax.
Seems to decrease the memory use by almost a factor 2...
* Bug: In Dijkstra::_cleanup(), as a double security, cleanup the queue.
* New: In Hurricane::Isobar::PySegment, added wrapper for getOppositeAnchor().
* Bug: CRL::PyRoutingLayerGauge, Python wrapper of getTrackPosition() was
in fact returning getTrackNumer().
* Bug: In Katana::PowerRailsPlanes::Rail::doLayout(), add the half minimum
distance to the blockage segments extensions. Was causing too near
VIAs is cmos45.
* Change: In cumulus/plugins/ClockTree, correctly manage routing gauge when
the lower pitches (M2/M3) is different from the upper one (M4/M5).
But we still can only do sxlib compliant gauges because we do not
handle a switch in preferred routing directions.
* Bug: In CRL::cyclop, on former versions of Qt 5 there was a double
link of the moc generated modules. This appears to be solved under
Ubuntu 10.04 LTS, so now we have to add them again explicitly.
* Bug: In Katana::Track::expandFreeInterval(), the OutsideElement case was
not handled correctly, the end index must be increased in that case.
As a result, this function was returning too short an interval.
This was affecting the computation of perpandicular free interval
in DataNegociate::update() for perpandicular fixed but not in a track.
* New: In Anabatic::NetBuilder and NetBuilderVH, now manage GCells with
one Pin, and up to three globals. Used to put terminals at the
edge of a block.
* New: In EtesianEngine, now manage placed Pins.
(done through extractInstanceName())
* Change: In CRL::RoutingGauge::getHorizontalGauge() no longer skip PinOnly
gauges to find the reference one (same goes for vertical).
* Bug: In Hurricane::DrawingQuery::drawGo(), forgot to apply translation
on Polygon and Rectilinear.
* Bug: In Hurricane::Rectilinear, forgot implementation of getContour().
Add a new accessor getPoints().
* Bug: In CRL::Blif::load(), do not always enforce translation towards
VHDL names. When loading LEF+gds it may change the Cell names between
the two stages so the gds layout do not get added to the LEF Cell
phantom.
Now add a boolean enforceVhdl argument (may be a flag in the future).
* Bug: In ::GdsStream::operator<<(Cell*), forgot to drive the Rectilinear.
* In Katana::RoutingEvent::_processRepair(), do no reschedule perpandiculars
that are already in repair mode, they may loop with repackperpandiculars().
Jean-Paul Chaput
Marie-Minerve Louërat