57 lines
1.9 KiB
TeX
57 lines
1.9 KiB
TeX
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\begin{itemize}
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\item Name : DpgenRam -- RAM Macro-Generator
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\item Description : Generates a RAM of \verb-regNumber- words of \verb-n- bits named \verb-modelname-.
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\item Terminal Names :
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\begin{itemize}
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\item ck : clock signal (input, 1 bit)
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\item w : write requested (input, 1 bit)
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\item selram : select the write bus (input, 1 bit)
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\item ad : the address (input, \verb-Y- bits)
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\item datain : write bus (input, \verb-n- bits)
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\item dataout : read bus (output, \verb-n- bits)
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\item vdd : power
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\item vss : ground
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\end{itemize}
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\item Parameters : Parameters are given with a map called \verb-param-.
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\begin{itemize}
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\item nbit : Defines the size of the generator
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\item nword : Defines the size of the words
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\end{itemize}
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% \item Behavior :
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%\begin{verbatim}
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%\end{verbatim}
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\item Example :
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\begin{verbatim}
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class myClass ( Model ) :
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def Interface ( self ) :
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self._ck = LogicIn ( "ck", 1 )
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self._w = LogicIn ( "w", 1 )
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self._selram = LogicIn ( "selram", 1 )
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self._ad = LogicIn ( "ad", 5 )
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self._datain = LogicIn ( "datain", 32 )
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self._dataout = TriState ( "dataout", 32 )
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self._vdd = VddIn ( "vdd" )
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self._vss = VssIn ( "vss" )
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def Netlist ( self ) :
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Inst ( 'DpgenRam'
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, param = { 'nword' : 32
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, 'nbit' : 32
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}
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, map = { 'ck' : self._ck
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, 'w' : self._w
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, 'selram' : self._selram
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, 'ad' : self._ad
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, 'datain' : self._datain
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, 'dataout' : self._dataout
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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\end{verbatim}
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\end{itemize}
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