\begin{itemize}
    \item Name : DpgenRam -- RAM Macro-Generator
    \item Description : Generates a RAM  of \verb-regNumber- words of \verb-n- bits named \verb-modelname-.
    \item Terminal Names :
    \begin{itemize}
        \item ck : clock signal (input, 1 bit)
        \item w : write requested (input, 1 bit)
        \item selram : select the write bus (input, 1 bit)
        \item ad : the address (input, \verb-Y- bits)
        \item datain : write bus (input, \verb-n- bits)
        \item dataout : read bus (output, \verb-n- bits)
        \item vdd : power
        \item vss : ground
    \end{itemize}
    \item Parameters : Parameters are given with a map called \verb-param-.
    \begin{itemize}
        \item nbit : Defines the size of the generator
        \item nword : Defines the size of the words
    \end{itemize}
%    \item Behavior :
%\begin{verbatim}
%\end{verbatim}
    \item Example :
\begin{verbatim}
class myClass ( Model ) :
  def Interface ( self ) :
    self._ck      = LogicIn  (      "ck",  1 )
    self._w       = LogicIn  (       "w",  1 )
    self._selram  = LogicIn  (  "selram",  1 )

    self._ad      = LogicIn  (      "ad",  5 )
    self._datain  = LogicIn  (  "datain", 32 )
    
    self._dataout = TriState ( "dataout", 32 )
    
    self._vdd   = VddIn    ( "vdd" )
    self._vss   = VssIn    ( "vss" )
    
  def Netlist ( self ) :
      
    Inst ( 'DpgenRam'
         , param = { 'nword'   : 32
                   , 'nbit'    : 32
                   }
         , map   = { 'ck'      : self._ck
                   , 'w'       : self._w
                   , 'selram'  : self._selram
                   , 'ad'      : self._ad
                   , 'datain'  : self._datain
                   , 'dataout' : self._dataout
                   , 'vdd'     : self._vdd
                   , 'vss'     : self._vss
                   }
         ) 
\end{verbatim}
\end{itemize}