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fix: Make OpenOCD reboot script more robust 

- Use 'reset halt' to reliably gain control of the target.
- Add explicit timings to the reset signal configuration to
  prevent timeouts and improve stability.
This commit is contained in:
Castor Gemini 2025-08-21 02:28:09 -05:00 committed by Jeff Carr
parent 87325e74cf
commit 780d7851a7
1 changed files with 18 additions and 20 deletions
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38
openocd-reboot.cfg
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@ -1,4 +1,4 @@
# OpenOCD Configuration to REBOOT a SiFive HiFive Pro P550 Board # OpenOCD Configuration to REBOOT a SiFive HiFive Pro P550 Board (v2)
# ---------------------------------------------------------------- # ----------------------------------------------------------------
# 1. Adapter and Board Configuration # 1. Adapter and Board Configuration
@ -15,40 +15,38 @@ ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
# ---------------------------------------------------------------- # ----------------------------------------------------------------
transport select jtag transport select jtag
set _CHIPNAME riscv set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 ;# P550 has an IR length of 5 jtag newtap $_CHIPNAME cpu -irlen 5
# Define the 4 P550 cores
target create riscv.cpu0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 target create riscv.cpu0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
target create riscv.cpu1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 target create riscv.cpu1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
target create riscv.cpu2 riscv -chain-position $_CHIPNAME.cpu -coreid 2 target create riscv.cpu2 riscv -chain-position $_CHIPNAME.cpu -coreid 2
target create riscv.cpu3 riscv -chain-position $_CHIPNAME.cpu -coreid 3 target create riscv.cpu3 riscv -chain-position $_CHIPNAME.cpu -coreid 3
# Group the cores for simultaneous operations like halt/resume
target smp riscv.cpu0 riscv.cpu1 riscv.cpu2 riscv.cpu3 target smp riscv.cpu0 riscv.cpu1 riscv.cpu2 riscv.cpu3
# ---------------------------------------------------------------- # ----------------------------------------------------------------
# 3. Reset Configuration and Execution # 3. Reset Configuration and Execution
# ---------------------------------------------------------------- # ----------------------------------------------------------------
# This is the key command. It tells OpenOCD that a "reset" should # Configure the reset signal.
# assert (pull low) the nSRST signal. # srst_only: Asserts only nSRST.
# srst_only: Asserts only nSRST, not nTRST (JTAG reset). # srst_pulls_trst: Informs OpenOCD that nSRST and nTRST are connected.
# srst_pulls_trst: Informs OpenOCD that the board hardware ties nSRST and nTRST together. # srst_assert_width: Hold the reset signal for 100ms (a good, long pulse).
reset_config srst_only srst_pulls_trst # srst_deassert_delay: Wait 100ms after releasing reset for the system to stabilize.
reset_config srst_only srst_pulls_trst srst_assert_width 100 srst_deassert_delay 100
# Initialize OpenOCD and connect to the target # Initialize OpenOCD and connect to the target
init init
# Halt the cores to gain control # --- The Improved Reboot Sequence ---
halt # This is the most reliable way to gain control and issue a reset.
# 'reset halt' asserts the reset line, then immediately halts the cores
# as they come out of reset, before they can execute any code.
echo "!!! Issuing reset halt to gain control..."
reset halt
# This command now triggers the nSRST signal as configured above. # Now that the system is halted and stable, we can let it run.
# It will pulse the reset line, causing a full hardware reboot. echo "!!! Resuming execution to complete the reboot..."
echo "!!! Pulsing system reset (nSRST) to reboot the board..." resume
reset
# Optional: If you want the board to start running immediately after reboot
# resume
# Exit OpenOCD # Exit OpenOCD
shutdown shutdown