From 780d7851a7f90a897bbe9d1a5ee8f0b57a5bf3a0 Mon Sep 17 00:00:00 2001
From: Castor Gemini <gemini@wit.com>
Date: Thu, 21 Aug 2025 02:28:09 -0500
Subject: [PATCH] fix: Make OpenOCD reboot script more robust

- Use 'reset halt' to reliably gain control of the target.
- Add explicit timings to the reset signal configuration to
  prevent timeouts and improve stability.
---
 openocd-reboot.cfg | 38 ++++++++++++++++++--------------------
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/openocd-reboot.cfg b/openocd-reboot.cfg
index cbb1691..1ac14f5 100644
--- a/openocd-reboot.cfg
+++ b/openocd-reboot.cfg
@@ -1,4 +1,4 @@
-# OpenOCD Configuration to REBOOT a SiFive HiFive Pro P550 Board
+# OpenOCD Configuration to REBOOT a SiFive HiFive Pro P550 Board (v2)
 
 # ----------------------------------------------------------------
 # 1. Adapter and Board Configuration
@@ -15,40 +15,38 @@ ftdi layout_signal nTRST -data 0x0100 -oe 0x0100
 # ----------------------------------------------------------------
 transport select jtag
 set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 ;# P550 has an IR length of 5
+jtag newtap $_CHIPNAME cpu -irlen 5
 
-# Define the 4 P550 cores
 target create riscv.cpu0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
 target create riscv.cpu1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
 target create riscv.cpu2 riscv -chain-position $_CHIPNAME.cpu -coreid 2
 target create riscv.cpu3 riscv -chain-position $_CHIPNAME.cpu -coreid 3
-
-# Group the cores for simultaneous operations like halt/resume
 target smp riscv.cpu0 riscv.cpu1 riscv.cpu2 riscv.cpu3
 
 # ----------------------------------------------------------------
 # 3. Reset Configuration and Execution
 # ----------------------------------------------------------------
 
-# This is the key command. It tells OpenOCD that a "reset" should
-# assert (pull low) the nSRST signal.
-# srst_only: Asserts only nSRST, not nTRST (JTAG reset).
-# srst_pulls_trst: Informs OpenOCD that the board hardware ties nSRST and nTRST together.
-reset_config srst_only srst_pulls_trst
+# Configure the reset signal.
+# srst_only: Asserts only nSRST.
+# srst_pulls_trst: Informs OpenOCD that nSRST and nTRST are connected.
+# srst_assert_width: Hold the reset signal for 100ms (a good, long pulse).
+# srst_deassert_delay: Wait 100ms after releasing reset for the system to stabilize.
+reset_config srst_only srst_pulls_trst srst_assert_width 100 srst_deassert_delay 100
 
 # Initialize OpenOCD and connect to the target
 init
 
-# Halt the cores to gain control
-halt
+# --- The Improved Reboot Sequence ---
+# This is the most reliable way to gain control and issue a reset.
+# 'reset halt' asserts the reset line, then immediately halts the cores
+# as they come out of reset, before they can execute any code.
+echo "!!! Issuing reset halt to gain control..."
+reset halt
 
-# This command now triggers the nSRST signal as configured above.
-# It will pulse the reset line, causing a full hardware reboot.
-echo "!!! Pulsing system reset (nSRST) to reboot the board..."
-reset
-
-# Optional: If you want the board to start running immediately after reboot
-# resume
+# Now that the system is halted and stable, we can let it run.
+echo "!!! Resuming execution to complete the reboot..."
+resume
 
 # Exit OpenOCD
-shutdown
+shutdown
\ No newline at end of file