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riscv-openocd/tcl
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Evgeniy Didin b2821b6074 Introduce tcl config files for Synopsys HSDK board 
With this commit we add tcl configure files
for ARCv2 HS Development kit(HSDK). HSDK board
has Quad-core ARC HS38 CPU with L1 and L2
caches.

Change-Id: I372ef45428c7c7ca1421a6da3e5ed08b86f705e0
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5784
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
 		2020-07-26 20:08:31 +01:00
..
board Introduce tcl config files for Synopsys HSDK board 2020-07-26 20:08:31 +01:00
chip coding style: tcl: remove empty lines at end of text files 2020-05-02 15:40:12 +01:00
cpld xilinx-xc7: Add additional IDCODEs. 2018-10-27 14:37:43 +01:00
cpu Introduce tcl config files for Synopsys HSDK board 2020-07-26 20:08:31 +01:00
fpga tcl: fix typo and spelling 2020-05-09 14:37:35 +01:00
interface Introduce tcl config files for Synopsys HSDK board 2020-07-26 20:08:31 +01:00
target Introduce tcl config files for Synopsys HSDK board 2020-07-26 20:08:31 +01:00
test coding style: tcl: remove empty lines at end of text files 2020-05-02 15:40:12 +01:00
tools tcl: fix typo and spelling 2020-05-09 14:37:35 +01:00
bitsbytes.tcl coding style: tcl: remove empty lines at end of text files 2020-05-02 15:40:12 +01:00
mem_helper.tcl mem_helper: add mrh command 2018-12-06 09:38:41 +00:00
memory.tcl Include start-of-region address 2020-02-15 15:30:55 +00:00
mmr_helpers.tcl tcl: fix typo and spelling 2020-05-09 14:37:35 +01:00