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274 Commits

Author SHA1 Message Date
Megan Wachs efd7260972 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-14 07:31:25 -07:00
Tim Newsome 909c9d4ab2 Conform to OpenOCD style 
Change-Id: I3954a8ac254b460560fa1414c5921777e4005645
 2018-05-03 17:58:44 -07:00
Tim Newsome 487501e761 Merge branch 'riscv' into optimize 
Change-Id: I2693eb05dee72acd2df5d8594c51e9da08ea1cc6
 2018-05-03 16:02:59 -07:00
Tim Newsome 292180fb44
Merge pull request #246 from darius-bluespec/sysbus-bugfix 
Bug fixes for system bus access
 2018-05-01 14:12:48 -07:00
Darius Rad 31494f68a4 Properly retry system bus access if busy error was detected. 2018-05-01 11:45:24 -04:00
Darius Rad cb282e81bc Fix polling for system bus busy. 2018-05-01 11:45:24 -04:00
Tim Newsome b62c014bdc Merge branch 'riscv' into notice_reset 2018-04-30 13:36:06 -07:00
Tim Newsome 9a69c1c096 Fix mingw32 build. 
Change-Id: If7a57749ba8c49385a4020ce8d2d8dbb94242122
 2018-04-20 16:28:24 -07:00
Tim Newsome 4593659edf Fix error messages for reset dmi timeouts. 
Change-Id: I00869ba20db6f27415af8e53e7b3e67741bf894d
 2018-04-20 15:10:56 -07:00
Megan Wachs eeac4f7fd4 riscv-compliance: remove whitespace 2018-04-19 10:52:19 -07:00
Megan Wachs debf2b040a riscv-compliance: correct the HALTSUM0/HALTSUM1 checks 2018-04-19 10:36:52 -07:00
Megan Wachs ac953c71c0 riscv-compliance: add dummy comments to appease the linter 2018-04-18 16:15:07 -07:00
Megan Wachs 06fc61f464 riscv-compliance: whitespace 2018-04-18 16:10:41 -07:00
Megan Wachs 3fedb7d97f Merge remote-tracking branch 'origin/riscv' into HEAD 2018-04-18 15:22:38 -07:00
Tim Newsome 005630d24d Use reset timeout to read dmstatus out of reset 
Change-Id: I74cc6a1e006269270c5197994d21523d01206141
 2018-04-18 14:31:00 -07:00
Tim Newsome 69a426038d
Enforce OpenOCD style guide. (#239) 
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
 2018-04-18 13:11:08 -07:00
Megan Wachs 8fa81c1f97 riscv-compliance... code that compiles > code that makes linter happy 2018-04-17 16:11:03 -07:00
Megan Wachs 8ce4f787ca riscv-compliance: whitespace cleanup 2018-04-17 16:05:15 -07:00
Megan Wachs 6217f56186 Merge remote-tracking branch 'origin/notice_reset' into riscv-compliance 2018-04-17 15:47:41 -07:00
Megan Wachs 401dcf7a06 riscv-compliance: make sure reset assertion and deassertion actually worked. 2018-04-17 15:47:15 -07:00
Megan Wachs f516825079 riscv-compliance: make sure not to clear DMACTIVE 2018-04-17 14:30:37 -07:00
Megan Wachs aef4888249 riscv-compliance: Fix writing hartsello 2018-04-17 11:55:50 -07:00
Megan Wachs 30e1dbdc6b riscv-compliance: fix compile errors and whitespace 2018-04-17 10:43:36 -07:00
Megan Wachs ef684c2e68 riscv-compliance: Incorporate feedback to make tests make fewer assumptions about hte implementation and properly use OpenOCD functions 2018-04-17 10:28:13 -07:00
Megan Wachs 716c12bcaf riscv: don't supporess errors 2018-04-17 07:57:32 -07:00
Megan Wachs 4c6c4cb078 riscv: Add a TODO note we need to handle hartselhi 2018-04-17 07:53:34 -07:00
Megan Wachs fa99b8e3b1 riscv-compliance: Fix OpenOCD lint checks 2018-04-17 07:49:06 -07:00
Megan Wachs ff365173a0 riscv-compliance: fix too-narrow constant 2018-04-12 17:31:23 -07:00
Megan Wachs 2deff1b2c9 riscv: hartsel-> hartsello (not supporting hartselhi yet) 2018-04-12 16:10:45 -07:00
Megan Wachs adf7dd7b5e Merge branch 'riscv' into riscv-compliance 2018-04-12 16:03:54 -07:00
Megan Wachs 7eca2dfe5d Squashed commit of the following: 
commit fb7009fc38
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 16:41:14 2018 -0800

    Make some error messages to be printed once

commit e09dd62229
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 15:30:10 2018 -0800

    Reduce severity of the error messages that are polluting the log

commit 73b6ea55eb
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 13:32:54 2018 -0800

    removed unused variable

commit c3bdcb0c4a
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 18:32:08 2018 -0800

    more R/O checks

commit 353cf212bd
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 14:27:25 2018 -0800

    write progbuf via DMI

commit e73d82e3d6
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 18:47:36 2018 -0800

    add writes to progbuf

commit f97e4b53e4
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 16:20:12 2018 -0800

    Try to zero out ROM
 2018-04-12 15:02:04 -07:00
Tim Newsome 1fda89c3ce Only write hartsel if we're changing it. 
DebugBreakpoint went from 2.94s to 2.74s.

Change-Id: Ia3ab857aea89fb83f0bcdd9a6bb69f256bde13dd
 2018-04-09 15:13:24 -07:00
Tim Newsome 238b1e9f06 Cache registers while halted. 
This saves us from re-reading s0 before doing just about anything
program buffer related.

Improves DebugBreakpoint from 3.01s to 2.89s. Feels like the improvement
should be larger than that. Maybe my metric isn't very good.

Change-Id: I85e1a1ddbf09006d76c451a32048be7b773dcfe9
 2018-04-06 15:52:40 -07:00
Tim Newsome 5c0a9a9ee4 Just read abstractcs once when executing a command 
DebugBreakpoint went from 3.41s to 3.05s!

Change-Id: Icfc4ad5fb663b3607bf2027fda744b43be662fc5
 2018-04-05 17:59:07 -07:00
Tim Newsome 6030644a9d Track misa per-hart even in -rtos mode 
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.

This fixes #194.

Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
 2018-04-03 15:12:19 -07:00
Tim Newsome 755c6a4caa Add wall clock timeout to dmi_op() 
If the target is held in reset we'd keep adding more delays, and since
those grow exponentially they'd get so huge it would take forever to
exit out of the loop.

Change-Id: Ieaab8b124c101fd1b12f81f905a6de22192ac662
 2018-03-30 15:24:16 -07:00
Tim Newsome 4ee7d5373d Fix auth error message. 
Change-Id: I79b72325e9a6b85f8b67df8e9837a54cfce928f0
 2018-03-30 13:21:00 -07:00
Tim Newsome 55e427b72b Don't rely on havereset when deasserting reset. 
This removes the need for the supports_havereset config option as well.

Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
 2018-03-27 11:31:39 -07:00
Tim Newsome c534a37fc3 Make reset work again for multicore 
Both regular multicore and RTOS hack methods.

Change-Id: I9a0998de0f33ef8a4d163f36ddf01c7675893b3d
 2018-03-23 12:53:24 -07:00
Tim Newsome d7282d0bfe Add set_supports_havereset 
This lets reset work on targets that don't implement havereset.

Change-Id: I09eb20970fac740eb6465541db6e739ae3e6b0d5
 2018-03-22 12:44:15 -07:00
Tim Newsome e5591c2584 Halt the target again if it was reset while halted 
Change-Id: I59707e7b2e1646c312d4eb8e96e9d7dfd1e128c2
 2018-03-20 12:34:17 -07:00
Tim Newsome 52eabbd2a5 Add `riscv set_prefer_sba` 
This allows a user to tell OpenOCD to prefer system bus access for
memory access, which can be useful for testing, or when there really is
a difference in behavior.

Change-Id: I8c2f15b89a2ccdae568c68ee743b75a74f9ad6bd
 2018-03-19 14:09:56 -07:00
Tim Newsome d5b450c508 Fix build, broken by b7c5c5d228. 
Change-Id: Iee55d799e14376ec5079d7db5fc6369e85368212
 2018-03-19 12:56:05 -07:00
Tim Newsome 40e0c5b976 Format error messages. 
Change-Id: I50c21319765e1ead279223466ed02a06ecf6a522
 2018-03-19 12:46:10 -07:00
Tim Newsome b7c5c5d228
Merge pull request #225 from riscv/old_bus2 
Support v0 System Bus Access
 2018-03-19 12:11:28 -07:00
Tim Newsome 4d2d1f7324 Notice when a hart has reset. 
Attempt to notify the user.
Deal correctly with a halted target that is suddenly running.

Change-Id: Ib0e0aa843d1da22df673713687ec884f6af14949
 2018-03-16 15:04:14 -07:00
Tim Newsome fd2759a63d Clear havereset in examine() and deassert_reset(). 
Change-Id: I89f32a44ebd6f3df0d0e2f6b54b111daa6ab06f7
 2018-03-16 15:03:31 -07:00
Tim Newsome 848062d0d1 Propagate errors in more places 
Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
 2018-03-16 15:03:31 -07:00
Tim Newsome 3ddbbd525d
Merge pull request #222 from riscv/dmi_commands 
Add riscv dmi_read/dmi_write commands.
 2018-03-15 11:32:33 -07:00
Tim Newsome 68a6812a41 Use TARGET_PRIxADDR instead of PRIx64. 
Change-Id: Iaf71a2d767ff4876b4cf1c9d546744ec6f97dda2
 2018-03-09 18:02:18 -08:00