interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,813 Commits 65 Branches 14 Tags 106 MiB
Commit Graph

9 Commits

Author SHA1 Message Date
Spencer Oliver e6b27756da armv7m: use generic register core_cache 
This removes the armv7m::core_cache and uses the generic arm::core_cache.

Change-Id: If854281b31486cea8be005008f6a71a691b4c208
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/968
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
 2013-02-02 16:22:04 +00:00
Spencer Oliver 85ed6ea59f armv7m: remove unused armv7m_regtype 
This simplifies the armv7m_core_reg structure ready for the move to using
the generic struct arm_reg.

Change-Id: I8edb9d77cc54965d49cd2e754568ebcea4cf6964
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/967
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
 2013-02-02 16:21:50 +00:00
Spencer Oliver fc2abe63fd armv7m: use generic arm::core_mode 
To simplify things change over to using the generic core_mode struct rather
than maintaining a armv7m specific one.

Change-Id: Ibf32b785d896fef4f33307fabe0d8eb266f7086f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/966
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
 2013-02-02 16:21:41 +00:00
Spencer Oliver 3eb7d77601 hla: enable DWT component and fix watchpoints 
The makes sure the DWT component is always enabled so that watchpoints
work as expected.

This does need merging into the existing cortex_m logic, however at the
moment this is non trivial.

Change-Id: Ic6cccd1badb51f70a2ca8ea9ab6923788a94c1bf
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1122
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
 2013-01-27 14:07:59 +00:00
Spencer Oliver 48e01a4969 hla: support setting DCB_DEMCR on resume 
This is only minimal support to enable use to catch a Hard Fault in
the stm32l flash bootloader.

Change-Id: I21d6a11893e2f1d173ebff1a651d6f52bf6eec32
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1103
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: jenkins
 2013-01-02 18:13:18 +00:00
Spencer Oliver c7a6f065d2 hla: add ability to configure read/write buffer size 
Other adapters (TI ICDI) that use this driver can use a larger
read/write buffer size than the original stlink could.

Change-Id: I9beb7748049097cbe29a2340799c450bd74e199d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/948
Tested-by: jenkins
 2012-12-23 21:46:10 +00:00
Spencer Oliver 561984c8f6 hla: fix watchpoints not being set 
Watchpoints were not being enabled when the hl adapter target was resumed.
This effects both stlink and icdi interfaces.

Change-Id: Ia9f8a9415be97a467cd099b63b6bc9f7f37d0c0d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/931
Tested-by: jenkins
 2012-12-23 21:46:02 +00:00
Spencer Oliver 6c467da586 stlink: rename stlink cmd names 
As part of the switch to using the hla for the stlink interface we rename
the cmds to a more generic name.

Update scripts to match new names.

Also add handlers for deprecated names.

Change-Id: I6f00743da746e3aa13ce06acfdc93c8049545e07
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/921
Tested-by: jenkins
 2012-12-23 21:45:42 +00:00
Spencer Oliver 549d9bc72c target: add deprecated target name support 
This enables us to change the target name without breaking any
target scripts.

Change-Id: I635f961e573264d3dab2560f3a803ef1986ccfde
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/919
Tested-by: jenkins
 2012-12-23 21:45:23 +00:00