crc check was always performed on newly flashed data, now it is optional
flash mem can be locked by writing a specific word to a specific address in flash.
to verify flash, target must be halted, and this will (when the new halt sequence is implemented) require reseting the chip. if the target is reset after writing the lock words, then it will lock, hence the CRC will fail because it is not possible to read stuff from the target.
also added a function that resets the jtag state machine.
this is not used yet, but will be soon.
it is implemented to allow strict control over JTAG state machine, necessary to implement to halt and unlocking sequences.
i had started my code from dsp5683xx, i renamed a bunch of stuff to names i consider to be better.
i believe no one is using this code, so nobody should be affected. (it's not too late to do this change)
before doing anything with the flash module (FM) the clock divider must be set.
if erase_check was the first thing done with the FM after reset then an error would be generated because the clk divider was not set.
now erase_check sets the clk divider.
reorganized code to get rid of compiler warnings
the warning were related to allignment, i do not get these warning on my build system (i've tried setting the compiler flag but it doesn't work, still working on why) so i cannot detect them (yet.)
cygwin does not define sleep, so use our internal win32 version.
caused by commit 9d4aec6bda
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Rodrigo L. Rosa
Øyvind Harboe
Spencer Oliver