Also avoid receiving data if the value is discarded on the call-site.
Change-Id: Ied87b551536a00d9fad469b9843cccae1976e6b6
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
* Register file examination is separated.
* Allow to access registers through cache as early as possible to re-use
general register access interface and propely track state of the
register.
* Reduces the number of operations: S0 and S1 are saved/restored only
when needed (targets without abstract CSR access).
Change-Id: I2e205ae4e88733a5c792f8a35cf30325c68d96b2
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
* Eliminates the use of VLA, which is prohibited by `doc/manual
/style.txt`:
Link: c6bb902629/doc/manual/style.txt (L164-L166)
* Unifies DMI access interface.
* Reduces code duplication.
Change-Id: I2d7b0595f171e21062049ff61f76fb5a3c992d11
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reduces the number of JTAG queue flushes.
Change-Id: Id103f5da1a3ea3177447046711e0e62a22c98c75
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit creates file structure for register cache related
functions.
Specifically:
* `riscv_reg.h` -- general interface to registers. Safe to use after
register cache initialization is successful.
* `riscv_reg_impl.h` -- helper functions to use while implementing
register cache initialization.
* `riscv_reg.c` -- definitions of functions from `riscv_reg.h` and
`riscv_reg_impl.h`.
* `riscv-011_reg.h` -- register cache interface specific to 0.11
targets.
* `riscv-013_reg.h` -- register cache interface specific to 0.13+
targets.
* `riscv-011/0.13.h` -- version-specific methods used to access
registers. Will be extended as needed once other functionality (not
related to register access) is separated (e.g. DM/DTM specific stuff).
Change-Id: I7918f78d0d79b97188c5703efd0296660e529f2a
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Without the selection the TAP can be left in bypass.
Change-Id: I79c6bf74802dc9c9475947d1787a3d0b797f3952
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This allows to eliminate up to two DMI NOPs.
Change-Id: I09a18bd896fce2392d1b65d4efb38b53e334a358
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Code cleanup: "slot_t" is unused in riscv013 - remove it.
Change-Id: I9d5a0cf8446a180b1d13a9ce2c86d904b946cf28
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
This would elliminate the need for an extra nop in-between the two reads
in case of a 64-bit register.
Change-Id: I2cddc14f7f78181bbda5f931c4e2289cfb7a6674
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
There was an error introduced by
8319eee9e1.
According to RISC-V Debug Spec 1.0.0-rc1 [3.14.2. Debug Module Contro]:
> 0 (inactive): The module’s state, including authentication mechanism,
takes its reset values (the dmactive bit is the only bit which can be
written to something other than its reset value).
`dmactive` was written together with `hartsel` and `hasel` in
8319eee9e1.
Change-Id: I11fba35cb87f8261c0a4a45e28b2813a5a086078
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit is related to testing how OpenOCD responds to `dmi.busy`.
Consider testing on Spike (e.g. `riscv-tests/debug` testsuite). Spike
returns `dmi.busy` if there were less then a given number of RTI cycles
(`required_rti_cycles`) between DR_UPDATE and DR_CAPTURE:
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/jtag_dtm.cc#L145https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/jtag_dtm.cc#L202
`required_rti_cycles` gets it's value from `--dmi-rti` CLI argument and
is constant throughout the run.
OpenOCD learns this required number of RTI cycles by starting with zero
and increasing it if `dmi.busy` is encountered. So the required number
of RTI cycles is learned during the first DMI access in the `examine()`.
To induce `dmi.busy` on demand `riscv reset_delays <x>` command is
provided. This command initializes `riscv_info::reset_delays_wait`
counter to the provided `<x>` value. The counter is decreased before a
DMI access and when it reaches zero the learned value of RTI cycles
required is reset, so the DMI access results in `dmi.busy`.
Now consider running a batch of accesses. Before the change all the
accesses in the batch had the same number of RIT cycles in between them.
So either:
* Number of accesses in the batch was greater then the value of
`riscv_info::reset_delays_wait` counter and there was no `dmi.busy`
throughout the batch.
* Number of accesses in the batch was less or equal then the value of
`riscv_info::reset_delays_wait` counter and the first access of the
batch resulted in `dmi.busy`.
Therefore it was impossible to encounter `dmi.busy` on any scan of the
batch except the first one.
Change-Id: Ib0714ecaf7d2e11878140d16d9aa6152ff20f1e9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This allows to merge the implementation in `batch.c` with the one in
`riscv-013.c`.
Change-Id: Ic3821a9ce2d75a7c6e618074679595ddefb14cfc
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
According to the RISC-V Debug Spec (1.0.0-rc1)[3.7 Abstract Commands]:
> While an abstract command is executing (busy in abstractcs is high), a
debugger must not change hartsel, and must not write 1 to haltreq,
resumereq, ackhavereset, setresethaltreq, or clrresethaltreq.
The patch ensures the rule is followed.
Change-Id: Id7d363d9fdeb365181b7058e0ceb0be0df39654f
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This allows to examine each DM ones (e.g. enumerating harts assigned to
the DM). Additionaly, it is guaranteed that the DM is reset before the
examination.
Change-Id: I2333d06ff1152bf51c647d59baa55cb402054cb9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
According to the RISC-V Debug Spec (1.0.0-rc1)[3.7 Abstract Commands]:
> While an abstract command is executing (busy in abstractcs is high), a
debugger must not change hartsel, and must not write 1 to haltreq,
resumereq, ackhavereset, setresethaltreq, or clrresethaltreq.
Tracking `abstractcs.busy` allows to enforce this rule.
Change-Id: If5975b48cf9fd379033268145c79103c36fb8134
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Fixes:
- Data types of address & data parameters in riscv_batch_add_*()
and riscv*_fill_dm*() changed to uint64_t and uint32_t.
- Corrected the comparison in riscv_batch_full().
- Corrected assertions in riscv_batch_get_dmi_read_op()
and riscv_batch_get_dmi_read_data().
Cleanup:
- Simplified calloc() fail handling in riscv_batch_alloc().
- Added explicit NULL assignments in riscv_batch_alloc()
for clarity and readability. Don't rely on calloc().
- Removed suffix `_u64` from riscv_*_fill_dm*() since it
does not have any meaning.
- Renamed *dmi_write_u64_bits() to *get_dmi_scan_length()
which better describes its purpose.
Change-Id: Id70e5968528d64b2ee5476f1c00e08459a1e291d
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Cleanup, non-functional changes:
- Replaced one call of low-level function dm_op()
by high-level dm_read().
- Made sure that truncation of values passed to dm_*
is explicit. (Added explicit casts.)
Change-Id: I1d1b2f29a822b6841373f3313de2b1e96f514116
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
This reverts commits 2e920a212f and
8dbb1250f5.
The reason is, after `openocd_is_shutdown_pending()` becomes true,
arbitrary command may be executed:
* In `target_destroy()` and the corresponding
`target->type->deinit_target()`.
* In user-specifyed `pre_shutdown_commands` list.
Change-Id: Icd00d1d954cd45e255880a6f76c3a74c098d6a17
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
The reason for the change is a conflict: `dcsr[5]` is `dcsr.v` in
current spec, but it is `dcsr.debugint` in 0.11. This causes `priv`
register to be read incorrectly.
Change-Id: If2d8fdcd8536afa4c7149c453101b00ce0df1ce0
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
There was an error in `dm_read`/`dm_write`: DMI address was checked
against DM registers disregarding DM base address.
To solve the issue `dmi_address()` function was introduced.
Change-Id: Ia3be619417b5f5b53db5dfe302db05170d6787c9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
The motivalion for the change:
* `riscv_hart_count()` is used only once to print the value into the log
during exmination.
* The returned value is a bit confusing: it's not the total number of
targets on the TAP. It is the number of targets accessable through the
same DM. So the name of the function is misleading.
* This value is already reported on `-d3` level.
So the function seems redundant and can be safely removed.
Change-Id: Iac9021af59ba8dba2cfb6b9dd15eebc98fe42a08
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
In loops that typically take longer time to complete, check if there is
a pending shutdown request. If so, terminate the loop.
This allows to respond to a signal requesting a shutdown during some
loops which do not return control to main OpenOCD loop.
Change-Id: Iace0b58eddde1237832d0f9333a7c7b930565674
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
I don't think there are any real bugs here, but at least this gives us a
clean slate moving forward.
Change-Id: I29c6c398c28dfe580f9a2deb3bdbcfc491a2ceb6
Signed-off-by: Tim Newsome <tim@sifive.com>
Evgeniy Naydanov
Evgeniy Naydanov
Jan Matyas
Emmanuel Blot
Tomas Vanek
Jan Matyas
Parshintsev Anatoly
Tim Newsome