Per current OpenOCD conventions, LOG_ERROR should not be printed
when ERROR_COMMAND_SYNTAX_ERROR is returned. OpenOCD will print
the command syntax to the user on its own.
Existing flags: 'enable_virtual' and 'enable_virt2phys' were
replaced with explicit translation drivers. Motivation:
(1) Having 'enable_virtual' and 'enable_virt2phys' flags set simultaneously
may cause double address translation which is unacceptable
(2) Flags were global for all targets which is wrong too
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
If some other TAP is not in BYPASS, an IR scan is needed to select
BYPASS on that TAP.
Change-Id: Iae425a415109b1a853db3718762661877eea56e8
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
See https://github.com/riscv-collab/riscv-openocd/issues/1139
riscv013_invalidate_cached_progbuf() was failing to zeroize the final
buffer array element. Use memset() instead of a manual loop to zeroize
it in order to address this and simplify the code.
These devices are essentially the same as the E54 series with the
exception of immutable boot (SG41, SG61) and HSM (SG60, SG61), and some
bug fixes found only in E54 revision F. When the security features are
not enabled, they behave identically except for the different DIDs.
Signed-off-by: Matt Trescott <mtc@melexis.com>
Change-Id: Ic93313f3e20af0ed4a5768880d17b335a7b7bb04
Reviewed-on: https://review.openocd.org/c/openocd/+/8355
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
(1) Error code and 'skip_reason' string were replaced with memory access
status. It allows to specify whether OpenOCD should exit the access
early.
(2) Slightly refactored 'read_memory' and 'write_memory' functions.
Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
Fixes#1043
There were multiple issuese with DMI logging:
1. Address was assumed to be the same (#1043).
2. Reported IDLE count was not affected by a reset of the delays.
3. VLA were used.
These issues are addressed in the commit.
Change-Id: I82f45505e8a62dfdd7dcb418784975fe10180109
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Use a command group 'telnet' with subcommands instead of individual
commands with 'telnet_' prefix. Even though there is only one subcommand
at the moment, make this change to ensure consistency with other commands.
The old command is still available to ensure backwards compatibility,
but are marked as deprecated.
Change-Id: I5e88632fa0d0ce5a8129e9fcf5ae743fc5b093cb
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8378
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The current semantics are a bit confusing, as the return value looks
like memcmp (0/false being equal) but the bool return type means one
likely expects true to mean equal. Make this clearer by switching them
out for buf_eq* functions that do that instead.
Checkpatch-ignore: UNSPECIFIED_INT
Change-Id: Iee0c5af794316aab5327cb9c168051fabd3bc1cb
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8490
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Backtraces performed by GDB on any thread other than the current
thread would fail if hardware 8 byte ISR stack alignment
was enabled on cortex_m targets. Stack reads now adjust
the stored SP to account for a potential offset introduced by hardware.
Fixed incorrect register offsets for cortex_m Nuttx frames by reading
the TCB info symbols to determine correct offsets.
Fixed offsets can no longer be used since the offsets have changed
multiple times for different Nuttx versions.
Tested on nuttx-12.1.0.
Tested using custom stm32h7 board and custom s32k148 board variants.
Built with CONFIG_ARCH_FPU enabled and disabled to
test FPU and non FPU frame logic.
Change-Id: Ifcbeefb0ddcfbcb528daa9d1d95732ca9584c9ef
Signed-off-by: daniellizewski <daniellizewski@geotab.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8180
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
When a target is reset we must invalidate register caches in order
to avoid showing stale register values or writing them back to
registers. Use EDPRSR.SR to detect a previous reset, and EDPRSR.R to
detect a current reset state.
Change-Id: Ia1e97d7154cf7789d392274eee475733086a835b
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8425
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
There was a conflict:
1. commit 2cd8ebf44d ("breakpoints: use 64-bit type for watchpoint mask
and value")
2. commit 0bf3373e80 ("target/breakpoints: Use 'unsigned int' for
length")
The second commit was created erlier, but merged later so the types of
`mask` and `value` became `uint32_t` in `watchpoint_add_internal()`.
This created a bug:
`WATCHPOINT_IGNORE_DATA_VALUE_MASK` is defined as `(~(uint64_t)0)`.
Truncation to uint32_t makes it so the comparisons with the constant
don't work.
Change-Id: I19c414c351f52aff72a60330d83c29db7bbca375
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This is the fast path for when there is a mismatch in the leading whole
bytes, which means we should return true to indicate not equal like all
the other cases here and in the surrounding functions. Otherwise we'll
incorrectly report _buf1 == _buf2 if and only if there are mismatches in
the leading whole bytes.
This was introduced during the refactor and optimisation referenced
below.
The only in-tree caller of this is jtag_check_value_inner, which will
just fail to catch some errors. However, downstream in riscv-openocd it
gets used in the riscv target to determine whether an IR scan is needed
to select the debug module, and with an IRLEN >= 8 this breaks resetting
if the encoding for the DMI isn't all-ones in its leading whole bytes
(to match BYPASS), since it will believe they are the same and not do an
IR scan, failing (with "At least one TAP shouldn't be in BYPASS mode")
in the subsequent DR scan due to the TAP still being recorded as having
bypass set (and really having an instruction of either BYPASS or
IDCODE).
Fixes: e4ee891759 ("improve buf_cmp and buf_cmp_mask helpers")
Change-Id: Ic4f7ed094429abc4c06a775eb847a8b3ddf2e2d6
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8489
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Two different sizes uint8_t and uint32_t was used for this value
without a good reason.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I4bb60cc5397ffd0d37e7034e3930e62793140c8d
Reviewed-on: https://review.openocd.org/c/openocd/+/8439
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Tested-by: jenkins
Could be handy for dummy transfer size detection.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ibb485218f6c2ff9066910bb58be0fc614b77add3
Reviewed-on: https://review.openocd.org/c/openocd/+/8438
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Use the TRAX interface DEBUGPC if available.
Otherwise use default stop-and-go profiling.
ESP32-S3, before this patch:
Internal: 8 samples/second
FT2232H: 12 samples/second
After this patch:
Internal: 18ksamples/second
FT2232H: 100ksamples/second
Change-Id: I681f0bccf4263c1e24f38be511e3b3aec8bf4d60
Signed-off-by: Richard Allen <rsaxvc@rsaxvc.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/8431
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Yurii Shutkin <yurii.shutkin@gmail.com>
Simplify the code using the target endianness independent API.
Change-Id: I39f720d0db9cf24eb41d7f359e4321bbc2045658
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8474
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Flash banks created in kinetis_create_missing_banks did not populate
bank->minimal_write_gap. The default value of 0 was interpreted as
FLASH_WRITE_CONTINUOUS. This created unnecessary large padding if your
binary had a gap in the populated flash. It also caused flash errors
when loading with GDB because the erroneously padded pages were not
erased first. Tested using an S32k148 using s32k.cfg.
Change-Id: I9b7af698e29ac2c4f5fc8ecd82fa7f4b1a0d43f1
Signed-off-by: daniellizewski <daniellizewski@geotab.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8463
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
When multiple jlink programmers are connected and no specific serial
or USB location is specified, print out the detected serial numbers.
Signed-off-by: Marcus Nilsson <brainbomb@gmail.com>
Change-Id: I280da2b85363f7054c5f466637120427cadcf7d1
Reviewed-on: https://review.openocd.org/c/openocd/+/8356
Reviewed-by: Mark Zhuang <mark.zhuang@spacemit.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Looks like 7f2d3e2925 introduced a regression by incorrectly assigning
threads. The title of the commit message says that the intention was to
"derive threadid from SMP index", this is not what happens, however.
Instead threadid is assigned based on an index of all examined targets
in an SMP group.
This introduces two logical errors.
*Error 1*
Here is the code that assigns threads to harts:
```
foreach_smp_target(head, target->smp_targets) {
struct target *curr = head->target;
if (!target_was_examined(curr))
continue;
threadid_t tid = threads_found + 1;
hwthread_fill_thread(rtos, curr, threads_found, tid);
```
Now, imagine a situation when we have two targets: `target.A` and
`target.B`. Let's assume that `target.A` is NOT examined (it could be
under reset, for example). Then, according to the algorithm when
assigning thread identifiers `target.B` will be assigned tid of 1. The
respected inferior on GDB side will be called `Thread 1`.
Now, imagine that `target.A` activates and succefully examined - OpenOCD
will re-assign thread identifiers. And now on GDB side `Thread 1` will
represent the state of `target.A`. Which is incorrect.
*Error 2*
The reverse mapping between `threadid` and targets does not take the
state of targets into account.
```
static struct target *
hwthread_find_thread(struct target *target, threadid_t thread_id)
...
threadid_t tid = 1;
foreach_smp_target(head, target->smp_targets) {
if (thread_id == tid)
head->target;
++tid;
}
```
So the constructed mapping is incorrect. Since in example above
`Thread 1` will get mapped to `target.A`.
*Solution:*
It seems that threadids should be assigned based on position of the
thread in an smp group disregarding the target state.
Change-Id: Ib93b7ed3bb03696afdf56a105b333e22b9ec69b5
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8471
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Mark Zhuang <mark.zhuang@spacemit.com>
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
hide_csrs should not emit warnings on an attempt to hide non-exitents CSR.
hide_csrs funcitonality is intended to be used for scenarios when we don`t
want certain groups of registers to be available in GDB. Typically this is
needed to simplify integration with various IDE. In such scenarious it may
be impractical/unfeseable to figure out which register is present on a
target. So reporting a situation when a user wants to hide a non-existent
register creates way too much noise. This commit reduces severity of
relevant debug message to LOG_TARGET_DEBUG
Change-Id: Icbb982c4bcce7586fe35b6b004d0874d6014d5a7
This reverts commit e56dc61697.
The reverted commit claims to be the same as
b201a5db23, but it's not -- it changes the
warning in `riscv_reg_impl_expose_csrs()` instead of the one in
`riscv_reg_impl_hide_csrs()`.
If no mask is given, the value in the option register is replaced
completely. If a mask is set, only those bits that are set in the mask
are transferred into the option register; the others remain unchanged.
Change-Id: If488a10f92d7dcc0e0f192aef5e67c255fd529c3
Signed-off-by: Ondřej Hošek <ondra.hosek@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8466
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Use mbstowcs() to get required length of wide character string and
include space for terminating null wide character.
Change-Id: I668de6f0acc9b3ec5aca033d870dd9ef354f9077
Signed-off-by: Marcus Nilsson <brainbomb@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8232
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Integer values are interpreted by TCL as decimal, binary, octal
or hexadecimal if prepended with '0d', '0b', '0o' or '0x'
respectively.
The case of '0' prefix has been interpreted as octal till TCL 8.6
but is interpreted as part of a decimal number by JimTCL and from
TCL 9.
Align str_to_buf() to latest TCL syntax by:
- addding support for '0d', '0b' and '0o' prefix;
- dropping support for '0' prefix.
Change-Id: I708ef72146d75b7bf429df329a0269cf48700a44
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8465
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Mark Zhuang
Evgeniy Naydanov
Farid Khaydari
Evgeniy Naydanov
Antonio Borneo
Tommy Murphy
Matt Trescott
zhusonghe
Marc Schink
Jessica Clarke
daniellizewski
Peter Collingbourne
Tomas Vanek
Richard Allen
Parshintsev Anatoly
Marcus Nilsson
Ondřej Hošek
Tim Newsome