committed so as to ease cooperation and to let it be improved
over time.
So far it supports:
- halt/resume
- registers inspection
- memory inspection/modification
I'm still getting up to speed with OpenOCD internals and AVR32 so code is a little
bit messy and I'd appreciate any feedback.
if a tap could not be _enabled_, the error message was
'failed to disable tap'. Fixed that. Also, display the failing
tap's name.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Clear the enable bits for all clocks that are not set explicitly.
This is done to increase robustness by removing pre-existing
state.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
The PLL pre- and postdividers seem to have enable bits, although
these are not mentioned in the chip documentation.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
The patch improves flash erase for STR9x in case of a full bank erase.
Then the chip erase command is used instead which improves speed significantly.
Also I think it might help if e.g. STR912 enters some state where flash banks are locked, and a chip erase command is the key for unlocking the flash.
ocd_ prefix is used internally in OpenOCD as a kludge more
or less to deal with the two kinds of commands that OpenOCD
has.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
The strange thing here with this board is that 16MHz kinda
works, but only 2MHz is really stable.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This patch adds support for the omapl138 target and preliminary support for the da850evm. The
target cfg file is based on the icepick routing done by the target/ti_dm6446.cfg file.
I have performed limited testing with this setup. I am posting this patch in the interest of
sharing cfg files and in the hopes that the experts on this list can correct errors I have made or
point out enhancements.
The testing I have performed is debugging uboot with gdb where I also use the following local.cfg
and gdbinit files. Debugging appears to work in so much as 'ni' works.
local.cfg:
gdb_memory_map disable
gdbinit:
target remote localhost:3333
set remote hardware-breakpoint-limit 2
set remote hardware-watchpoint-limit 2
monitor poll on
Comments welcome.
Best Regards,
Ben Gardiner
if polling is off, then "reset run + halt" would fail
since halt incorrectly assumed the target was in the
reset state as it is the internal poll implementation
that moves the sw tracking of the target state out
of the reset state.
To reproduce:
> reset run; halt
JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
back-off algorithm for polling. Double polling
interval up to 5000ms when it fails.
when polling succeeds, reset backoff.
This avoids flooding logs(as much) when working
with conditions where the target polling will fail.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Clarify that ICDI is the generic logic, but this config is
for the JTAG-only (no-SWD) mode.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Hi everyone. I noticed some incorrect information in the user manual
regarding how the vector table is handled on the xscale, so for your
consideration, here's a short patch that corrects it, and adds a
little more detail I thought might be helpful.
The documentation states that OpenOCD does not attempt to synchronize
the vector tables in memory with those stored in the "mini instruction
cache". In fact, on each resume it does copy from memory to the cache
all entries in the high and low tables that were not previously
defined using the 'xscale vector_table' command. (In
src/target/xscale.c, see xscale_update_vectors(), which is invoked by
xscale_resume().) I take advantage of this during Linux boot-up. The
extra detail describes in general terms how I do this.
Corrections, comments are of course gratefully received.
Thanks,
Mike
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
It is useful to know that the printed errors are *all* the
errors there were.
Added missing error handling(found by inspection).
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
it can be useful to throttle performance: test
differences in behavior, test performance effect
of long roundtrips.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
srst_pulls_trst is only true on some (broken) LPC2148 boards, a fact
which is already documented in doc/openocd.texi, so it shouldn't be
set unconditionally in the target tcl.
This patch was needed to reflash when an Abort exception occured very
early after reset, before OpenOCD tried to halt the CPU.
This flash driver works on more than just two chips.
(Though it does need work still, e.g. to protect more than 64K.
(On non-'3748-A0 chips where errata allow that.))
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make it scriptable, so code can be conditionalized based on
what transport is in use for the session.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
For the above targets the exit_point is
optional when used with run_algorithm, so remove it.
This makes updating the algorithm less error prone.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
As the mips32 uses instruction breakpoints for algorithms we do not really
need to check the pc on exit.
This now matches the behaviour of the arm codebase.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
As the armv7m uses instruction breakpoints for algorithms we do not really
need to check the pc on exit.
This now matches the behaviour of the arm4_5 codebase.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Update the arm_checksum_memory and arm_blank_check_memory
algorithms to use a breakpoint instruction on v5 arch.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Oleksandr Tymoshenko
David Brownell
Catalin Patulea
Øyvind Harboe
Piotr Esden-Tempski
Thomas Koeller
Fredrik Hederstierna
Ben Gardiner
David Brownell
Mike Dunn
Peter Stuge
Michal Demin
Spencer Oliver