Commit Graph

3972 Commits

Author SHA1 Message Date
oharboe 5a824c934f Fix NPE in GDB_EVENT_END as logforwarding was not disabled early enough
git-svn-id: svn://svn.berlios.de/openocd/trunk@2570 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-27 18:56:43 +00:00
oharboe e9b919fbc6 add "dummy" interface trick to the BUGS reporting suggestions
git-svn-id: svn://svn.berlios.de/openocd/trunk@2569 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-27 14:46:49 +00:00
oharboe e31e6a10de David Brownell <david-b@pacbell.net> More testcase work:
A5.3.11 Data processing (shifted register)

The usual kinds of problems; the most noteworthy were that
the "S"et flags bit was mis-handled in these instructions.
---
This is the last patch from a quickie set of tests covering all
encodings of the instructions with 32-bit opcodes.  There may
be some corner cases left, plus the instructions that aren't
yet handled, but the Thumb2 disassembler is no longer just
"lightly" tested with GCC output ... the new code paths have
mostly been verified.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-26 20:00:39 +00:00
oharboe 49e2267f1f More instruction decoding fixes:
A5.3.5 Load/store multiple
       A5.3.7 Load word

There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos.  Load word had two bitmask goofs.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-26 19:59:33 +00:00
oharboe 3bcf8a8a25 David Brownell <david-b@pacbell.net> More fixes from test cases:
A5.3.8 Load halfword, unallocated memory hints

It's mostly the usual sort of bitmasking goofage and getting the
width specs right.  In one case an older x86 GCC generated bad code
unless I structred a conditional differently (sigh).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-26 19:58:25 +00:00
oharboe fc318c0298 David Brownell <david-b@pacbell.net> More instruction decoding fixes:
A5.3.5 Load/store multiple
       A5.3.7 Load word

There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos.  Load word had two bitmask goofs.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-26 19:56:58 +00:00
oharboe 67dbf35896 David Brownell <david-b@pacbell.net> More instruction decoding fixes based on test cases, covering
ARMv7-M arch manual:

 A5.3.1 Data processing (modified immediate)
 A5.3.3 Data processing (plain binary immediate)
 A5.3.4 Branches and miscellaneous control

and other (immediate) encodings referenced there.  Several of
these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but
there were a few bugs too.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-24 16:49:44 +00:00
oharboe ad3a24f944 David Brownell <david-b@pacbell.net> Bugfix some instruction decoding ... I've crafted asm files
with testcases covering several new encodings in these sections
of the ARMv7-M arch manual:

 A5.3.12 Data processing (register)
 A5.3.13 Miscellaneous operations
 A5.3.14 Multiply, and multiply accumulate
 A5.3.15 Long multiply, long multiply accumulate, and divide

The issues were mostly in '12 and '13; some new related 16-bit
opcodes had issues too.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-24 16:48:12 +00:00
oharboe 431925a452 Andreas Fritiofson <andreas.fritiofson@gmail.com> I noticed there are a few checks for (rt == 0xf) even though that case
is handled with an early return at the top of the function.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2562 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-24 05:42:45 +00:00
oharboe 50aa561796 David Brownell <david-b@pacbell.net> thumb2 disassembly for Load halfword
git-svn-id: svn://svn.berlios.de/openocd/trunk@2561 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-23 15:35:16 +00:00
oharboe 31b520c379 David Brownell <david-b@pacbell.net> thumb2 disassembly for Load byte, memory hints
git-svn-id: svn://svn.berlios.de/openocd/trunk@2560 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-23 15:34:03 +00:00
oharboe c7565cc381 Ferdinand Postema <ferdinand@postema.eu> fix cygwin warnings
git-svn-id: svn://svn.berlios.de/openocd/trunk@2559 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-23 07:04:21 +00:00
oharboe 30b1bbceea David Brownell <david-b@pacbell.net> fix warnings
git-svn-id: svn://svn.berlios.de/openocd/trunk@2558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-23 07:02:43 +00:00
oharboe 7986ed5ac2 Jonathan Cameron <jic23@cam.ac.uk> fix regression from 1836 when the reset_config command was removed from pxa270.cfg
git-svn-id: svn://svn.berlios.de/openocd/trunk@2557 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-22 19:35:23 +00:00
oharboe a7a1ae032b Stefano Voulaz <s.voulaz@projecktstudio.com> first cut samsung_s3c2450
git-svn-id: svn://svn.berlios.de/openocd/trunk@2556 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-22 14:25:56 +00:00
ntfreak d460a7cd6c David Brownell <david-b@pacbell.net>:
Dump SP on poll, and show whether it's MSP or PSP.

Thread mode can use either stack pointer, so this is
part of the state that's not yet displayed.

Shrink some lines.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-21 20:19:02 +00:00
ntfreak 4da019edeb David Brownell <david-b@pacbell.net>:
Clean up treatment of registers in ARMv7-M and Cortex-M3. 

 - At the arch level:
    * Just list registers and names; don't impose core-specific
      policy about how they are accessed.
    * Each register has a symbol.
    * Remove the register mode field (irrelevant to debugger)

 - At the core/implementation level:
    * Just map the registers to their relevant access methods;
      don't require the arch level to say how that should work
      (cores other than Cortex-M3 could do it differently).
    * Don't use undefined bits from register 20.
    * Use register IDs that are part of the ARMv7-M interface.

In short, there's now a real distinction between the arch
and core layers.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-21 20:15:11 +00:00
ntfreak eea0486263 David Brownell <david-b@pacbell.net>:
Minor updates to the Thumb2 disassembly:

 - Bugfixes:
    * Distinguish branch from misc via "!=" not "=="
    * MRS register shift is 8 bits (vs MSR being 16)
 - Format tweaks:
    * CPS needed tab (not space)
    * add commma before some shifts
    * add space after comma in LDM/STM
    * use ".W" width spec on various instructions

git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-21 20:05:05 +00:00
ntfreak cd0ca916b3 David Brownell <david-b@pacbell.net>:
Revert parts of the previous ARMv7-M register patch.
It turns out that part of the issue is a documentation
problem for the Cortex-M3 r1 parts. So for the rest,
simpler fixes are possible (in followup patch).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-21 20:03:17 +00:00
ntfreak 55b1ea1d8e - fix issue with reading device id, bug appeared when flash_address code was added
- fix issue when multiple flash chips are connected, eg. x16 x 2 on 32bit mcu bus

git-svn-id: svn://svn.berlios.de/openocd/trunk@2551 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-20 07:03:11 +00:00
oharboe f703322b3f aduc flash problems have been resolved
git-svn-id: svn://svn.berlios.de/openocd/trunk@2550 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-19 19:31:54 +00:00
oharboe 8b994145b8 Andreas Fritiofson <andreas.fritiofson@gmail.com> UTF8 fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@2549 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-17 19:54:25 +00:00
oharboe 14cbd545bf added item to come up with slick new 32 bit jtag_add_xxx() API
git-svn-id: svn://svn.berlios.de/openocd/trunk@2548 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-16 10:44:42 +00:00
oharboe bd4377194e microscopic whitespace cleanup
git-svn-id: svn://svn.berlios.de/openocd/trunk@2547 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-16 10:43:15 +00:00
oharboe 4deb8530c6 microscopic white space fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@2546 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-16 10:30:50 +00:00
ntfreak 4ebd353ae1 - disable using parport ppdev under win32 hosts
git-svn-id: svn://svn.berlios.de/openocd/trunk@2545 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-16 10:03:33 +00:00
zwelch 1af6b72fc1 Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:
Move the dap command handler implementations to arm_adi_v5.c,
leaving just thin wrappers in armv7m.c.  There should be no
change in functionality here.  (From Magnus.)

Minor style cleanup:  whitespace, line length, etc.  Update spec
references to use docs which are currently available.  (From Dave.)


git-svn-id: svn://svn.berlios.de/openocd/trunk@2544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-16 00:08:36 +00:00
zwelch 16e17ab1b3 Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:
Some cleanup of the ARMv7-M support:

 - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
   update the Cortex-M3 doc refs (DDI 0337C is no longer available).

 - Those registers aren't actually general, and some are incorrect (per all
   public docs anyway).  Update comments and code accordingly.

     * What the Core Debug facility exposes is *implementation-specific*
       not architectural.  These values aren't fully portable.  They match
       Cortex-M3 ... so no current implementation will make trouble, but
       the next v7m implementation might.

     * Four of the registers are actually not exposed that way.  Before
       Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
       In that newest silicon, they are four bytes in one register, not
       four separate registers.

 - Update the CM3 code to report when that one register is available,
   and not try to access it when it isn't.  Also declare the register
   numbers that an eventual MRS/MSR solution will need to be using.

 - Stop line wrapping the exception labels.

So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.

Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts.  Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-16 00:08:21 +00:00
zwelch 0c2ff267aa David Brownell <david-b@pacbell.net>:
More 32-bit Thumb2 instruction decoding:

	A5.3.7 Load word 


git-svn-id: svn://svn.berlios.de/openocd/trunk@2542 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:49:12 +00:00
zwelch fdfd434c24 David Brownell <david-b@pacbell.net>:
More 32-bit Thumb2 instruction decoding:

	A5.3.12 Data processing (register)


git-svn-id: svn://svn.berlios.de/openocd/trunk@2541 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:49:05 +00:00
zwelch 00adcc773a David Brownell <david-b@pacbell.net>:
More 32-bit instruction decoding:

	A5.3.11 Data processing (shifted register)


git-svn-id: svn://svn.berlios.de/openocd/trunk@2540 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:49:00 +00:00
zwelch 930269b483 David Brownell <david-b@pacbell.net>:
More instructions decoded:

	A5.3.5 Load/store multiple 

The preferred PUSH/POP syntax is shown when appropriate.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2539 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:48:54 +00:00
zwelch 421b8e133a David Brownell <david-b@pacbell.net>:
More instructions decoded:

	A5.3.14 Multiply, and multiply accumulate 
	A5.3.15 Long multiply, long multiply accumulate, divide

The EABI requires *adjacent* register pairs, but the long multiply
ops can use any pair of registers; interesting.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2538 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:48:43 +00:00
zwelch 889bd3e716 David Brownell <david-b@pacbell.net>:
More Thumb2 32-bit opcode support:

	 A5.3.10 Store single data item 

Byte, word, halfword.  Offset, pre-index, post-index.  And
a "make like you're unprivileged" option when using small
immediate offsets.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2537 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:48:37 +00:00
zwelch 84e86e9aee David Brownell <david-b@pacbell.net>:
Print old-style Thumb NOP instructions as such.  (GCC uses "mov r8, r8"
instead of the architected NOP which is new in Thumb2.)


git-svn-id: svn://svn.berlios.de/openocd/trunk@2536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:48:32 +00:00
zwelch d2088f0d29 David Brownell <david-b@pacbell.net>:
Make disassembly of the Thumb load-literal instruction show the
address of the literal being loaded (so users can avoid doing
that math themselves).  Add and use an Align(PC,4) utility.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2535 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:48:27 +00:00
zwelch f163d0009d David Brownell <david-b@pacbell.net>:
Make the Thumb2 disassembler handle more 32-bit instructions:

  A5.3.3 Data processing (plain binary immediate)

These use mostly twelve bit literals, but there are also bitfield
and saturated add primitives.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2534 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:48:21 +00:00
zwelch 0165ae4405 David Brownell <david-b@pacbell.net>:
Make the Thumb2 disassembler handle more 32-bit instructions:

  A5.3.1 Data processing (modified immediate)

My small sample shows GCC likes to use many of these instructions.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2533 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:48:16 +00:00
zwelch 8b89224c6e David Brownell <david-b@pacbell.net>:
Make the Thumb2 disassembler handle a bunch of 32-bit instructions:

  A5.3.4 Branches and miscellaneous control
 
Note that this shifts some responsabililty out of helper functions,
making the code and layout simpler for 32-bit decoders:  they only
need to know how to format the instruction and its parameters.

Also, technical note:  with this patch, Thumb1 decoders could now
call the Thumb2 decoder if they wanted to get nicer treatment of
the exiting 32-bit B/BLX instructions.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2532 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:48:11 +00:00
zwelch b71e3aff6d David Brownell <david-b@pacbell.net>:
Change layout of Thumb disassembly to work better with Thumb2:

 - Move opcode to the left, allowing space for four hex bytes:
    * after address, two spaces not one tab (taking 6 spaces)
    * after 2-byte opcode, four spaces before tab
 - Also, after opcode mnemonic use a tab not a space, to make
   operands line up

Sample output (after some patches decoding a few 32-bit instructions):

0x00003e5a  0xf4423200	ORR	r2, r2, #131072	; 0x20000
0x00003e5e  0x601a    	STR 	r2, [r3, #0x0]
0x00003e60  0x2800    	CMP	r0, #0x00
0x00003e62  0xd1f3    	BNE	0x00003e4c
0x00003e64  0xf008fa38	BL	0x0000c2d8

The affected lines of code now wrap at sane margins too.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2531 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:39:48 +00:00
zwelch 309870e414 David Brownell <david-b@pacbell.net>:
Initial support for disassembling Thumb2 code.  This works only for
Cortex-M3 cores so far.  Eventually other cores will also need Thumb2
support ... but they don't yet support any kind of disassembly.

 - Update the 16-bit Thumb decoder:
 
     * Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added
       by ARMv6.  (It already seems to treat CPY as MOV.)

     * Understand CB, CBNZ, WFI, IT, and other opcodes added by
       in Thumb2.

 - A new Thumb2 instruction decode routine is provided.
 
     * This has a different signature:  pass the target, not the
       instruction, so it can fetch a second halfword when needed.  
       The instruction size is likewise returned to the caller.

     * 32-bit instructions are recognized but not yet decoded.
   
 - Start using the current "UAL" syntax in some cases.  "SWI" is
   renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM".

 - Define a new "cortex_m3 disassemble addr count" command to give
   access to this disassembly.

Sanity checked against "objdump -d" output; a bunch of the new
instructions checked out fine.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 23:39:37 +00:00
oharboe 2ff59c9aaf print errno when parport fails to open.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2529 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 12:30:06 +00:00
oharboe e76fe13a95 retire Eclipse settings, charset will be set elsewhere.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2528 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-15 06:43:28 +00:00
oharboe d78d79aff6 Eclipse settings include charset.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2527 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-14 18:30:00 +00:00
oharboe 8b82de60c7 David Brownell <david-b@pacbell.net> mention udev, and correct D2XX speed mentions
git-svn-id: svn://svn.berlios.de/openocd/trunk@2526 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-14 18:24:59 +00:00
ntfreak 1df358855a - fix small typo in documentation
git-svn-id: svn://svn.berlios.de/openocd/trunk@2525 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-14 11:57:59 +00:00
oharboe 197a195191 1.54 snapshot
git-svn-id: svn://svn.berlios.de/openocd/trunk@2523 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-14 10:38:26 +00:00
zwelch 4eb2e50e4d Archive released NEWS file: NEWS -> NEWS-0.2.0
Create new NEWS file from release script template.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2522 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-14 09:02:00 +00:00
zwelch f9c65b5cd5 Bump minor version and add tag:
Bump minor package version number: 0.2.0 -> 0.3.0
Add '-in-development' version tag: 0.3.0 -> 0.3.0-in-development

git-svn-id: svn://svn.berlios.de/openocd/trunk@2521 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-14 08:54:36 +00:00
zwelch 64d998e584 Remove '-in-development' version tag: 0.2.0-in-development -> 0.2.0
git-svn-id: svn://svn.berlios.de/openocd/trunk@2517 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-07-14 08:53:40 +00:00