This change is a quick-and-dirty workaround for the problem when user
wants to expose CSR with address "0" and instead of user-specified name
"csr0" was used.
The problem looks as follows:
riscv013_reg_examine_all eventually calls init_cache_entry for all CSRs.
init_cache_entry eventually results in a call to riscv_reg_gdb_regno_name.
Then in case of non-standard CSRs we have the following logic:
```
// NULL when regno == 0, since names are not generated yet
if (info->reg_names[regno])
return info->reg_names[regno]
...
if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095) {
// generate names for all exposed CSRs (the function
// lazy-initializes all the required names)
init_custom_csr_names(target);
// And here we have an error, since we overwrite the name generated
// by init_custom_csr_names
info->reg_names[regno] =
init_reg_name_with_prefix("csr", regno - GDB_REGNO_CSR0);
...
```
The error happens because when initially this function is called with
regno = 0, the first condition false, so we have to go and generate all
the names.
These fields duplicate the info in the corresponding register cache
entries.
Change-Id: Ic0d264e78c527e92bb069258ce39b614d8f5bcde
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
* Registers were not invalidated if the hart became unavailable.
* Improved logging in the case register invalidation involves loss of
information.
Change-Id: Icfb5e190dd6dcb1a97e4d314d802466cab7a01e4
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
hide_csrs should not emit warnings on an attempt to hide non-exitents CSR.
hide_csrs funcitonality is intended to be used for scenarios when we don`t
want certain groups of registers to be available in GDB. Typically this is
needed to simplify integration with various IDE. In such scenarious it may
be impractical/unfeseable to figure out which register is present on a
target. So reporting a situation when a user wants to hide a non-existent
register creates way too much noise. This commit reduces severity of
relevant debug message to LOG_TARGET_DEBUG
Change-Id: Icbb982c4bcce7586fe35b6b004d0874d6014d5a7
This reverts commit e56dc61697.
The reverted commit claims to be the same as
b201a5db23, but it's not -- it changes the
warning in `riscv_reg_impl_expose_csrs()` instead of the one in
`riscv_reg_impl_hide_csrs()`.
* Register file examination is separated.
* Allow to access registers through cache as early as possible to re-use
general register access interface and propely track state of the
register.
* Reduces the number of operations: S0 and S1 are saved/restored only
when needed (targets without abstract CSR access).
Change-Id: I2e205ae4e88733a5c792f8a35cf30325c68d96b2
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit creates file structure for register cache related
functions.
Specifically:
* `riscv_reg.h` -- general interface to registers. Safe to use after
register cache initialization is successful.
* `riscv_reg_impl.h` -- helper functions to use while implementing
register cache initialization.
* `riscv_reg.c` -- definitions of functions from `riscv_reg.h` and
`riscv_reg_impl.h`.
* `riscv-011_reg.h` -- register cache interface specific to 0.11
targets.
* `riscv-013_reg.h` -- register cache interface specific to 0.13+
targets.
* `riscv-011/0.13.h` -- version-specific methods used to access
registers. Will be extended as needed once other functionality (not
related to register access) is separated (e.g. DM/DTM specific stuff).
Change-Id: I7918f78d0d79b97188c5703efd0296660e529f2a
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Anatoly Parshintsev
Parshintsev Anatoly
Evgeniy Naydanov