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11 Commits

Author SHA1 Message Date
Omair Javaid f18ca510b3 Support for Arm VFP v3 registers read/write 
This patch adds support in openOCD to read/write Arm vector/floating 
point registers. This is compatible with Arm vfp v3 target xml in GDB. 
Please refer to binutils-gdb/gdb/features/arm/arm-vfpv3.xml

Change-Id: Id4dd1bddef51c558f1a86300c1a876d159463f18
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/4421
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
 2018-03-10 14:25:10 +00:00
Marc Schink d4b7cbff88 Make #include guard naming consistent 
Change-Id: Ie13e8af0bb74ed290f811dcad64ad06c9d8cb4fa
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2956
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
 2016-05-24 22:30:55 +01:00
Marc Schink d0e763ac7e Remove FSF address from GPL notices 
Also make GPL notices consistent according to:
https://www.gnu.org/licenses/gpl-howto.html

Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3488
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
 2016-05-24 22:30:01 +01:00
Spencer Oliver 08d4411b59 update files to correct FSF address 
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1426
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
 2013-06-05 19:52:42 +00:00
Evan Hunter 927e53f8d5 cortex_a : optimize apb read/write access. 
Rewrite: Adheres more closely to 'fast read/write' examples in TRM.
up to 50x faster

Change-Id: Ieb4da57d8367628f3e7306827a5b1f0ab550e641
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/903
Tested-by: jenkins
Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
 2013-03-15 15:50:42 +00:00
Spencer Oliver 9b3224e887 build: remove src file execute permission 
Change-Id: I42a250cdfcd03424a63cd1a255f9cf4a3c6e3ccd
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/671
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
 2012-05-28 11:59:37 +00:00
Spencer Oliver 374127301e build: cleanup src/target directory 
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/430
Tested-by: jenkins
 2012-02-06 11:00:36 +00:00
Luca Ellero 81f238f522 Add opcodes for load/store registers words immediate post-indexed 
Signed-off-by: Luca Ellero <lroluk@gmail.com>
 2011-04-13 21:32:24 +02:00
David Brownell 29a8cdc3b0 ARM: update arm_opcodes.h copyright 
I neglected to copy Magnus' copyright when I moved several
declarations from the ARMv7-M header.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
 2009-12-09 21:43:23 -08:00
David Brownell 910dd664ce Comment and doxygen fixes 
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
 2009-12-09 10:25:52 -08:00
David Brownell a4a2808c2a ARM: move opcode macros to <target/arm_opcodes.h> 
Move the ARM opcode macros from <target/armv4_5.h>, and a few
Thumb2 ones from <target/armv7m.h>, to more appropriate homes
in a new <target/arm_opcodes.h> file.

Removed duplicate opcodes from that v7m/Thumb2 set.  Protected
a few macro argument references by adding missing parentheses.

Tightening up some of the line lengths turned up a curious artifact:
the macros for the Thumb opcodes are all 32 bits wide, not 16 bits.
There's currently no explanation for why it's done that way...

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
 2009-12-07 14:57:43 -08:00