This is a proof of concept to get access to the debug port of a
secured kinetis cpu. On full flash erase the cpu is automatically
secured and the debug port is not accessible.
To get this to work the srst line is needed and the necessary
configuration should be added to the configuration file.
The driver sends ascii encoded bitbang commands over unix sockets or TCP to
another process. This driver is useful for debugging software running on
processors which are being simulated.
added an attempt to use the non-reseting halting sequence. if it fails, then the full sequence will be attempted. this makes things a bit faster most of the time.
changed the location of a function, avoiding a forward def
added an alternative way to enter debug mode, which does not require restarting the chip.
this will not always work, but in general it will (failure 0.3%), and failure is not a dramatic issue, simply have to use the full sequence.
the user can only access "halt", which uses the full sequence, so the user should not have any problems.
restarting the chip requires reconfiguring the flash module. the doc is very poor, so i'd rather have the two methods, and live with the 0.3%.
sometimes the master tap will be enabled, since tap switching is required during halt/lock/unlocking procedures.
now irscan handles this, avoiding unnecessary warnings and preventing errors.
got new info regarding setting the chip to debug mode, and locking/unlocking flash memory.
the newer implementation is a bit slower, but always works.
the previous implementation would randomly (as once every 25k-70k times) get the chip into a state where the freescale tool would be necessary. this is fixed now.
added functions to play around with the jtag state machine. they are not the happiest, but are necessary to be able to execute the halting/locking/unlocking sequences.
Conflicts:
src/target/dsp5680xx.c
the user can execute halt, but no enter_debug_mode. modified the error handling to suite this.
the new implementation of unlocking will use enter_debug_mode, and should not get the same errors as the user would, because not being able to enter debug mode is actually success when checking for locked flash.
crc check was always performed on newly flashed data, now it is optional
flash mem can be locked by writing a specific word to a specific address in flash.
to verify flash, target must be halted, and this will (when the new halt sequence is implemented) require reseting the chip. if the target is reset after writing the lock words, then it will lock, hence the CRC will fail because it is not possible to read stuff from the target.
also added a function that resets the jtag state machine.
this is not used yet, but will be soon.
it is implemented to allow strict control over JTAG state machine, necessary to implement to halt and unlocking sequences.
Currently the board/redbee-*.cfg files incorrectly include the
interface definition. Move the interfaces to interface/,
and create a single board/redbee.cfg that is common to both boards.
Intended usage is now:
openocd -f interface/redbee-econotag.cfg -f board/redbee.cfg
Posted by telekatz@gmx.de in the bettyhacks forum for openocd
0.4.0 and integrated into 0.5.0 by Gunnar Henne.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
buspirate has never supported building on native windows (mingw).
configure will now check this is not the case.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
AC_CHECK_FILE will die when cross-compiling. So don't use it to test the existence of guess-rev.sh.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Mathias K
Luca Bruno
Uwe Bonnes
Richard Uhler
Martin Schmölzer
Rodrigo L. Rosa
Øyvind Harboe
simonqian.openocd
Heythem Bouhaja
Evan Hunter
Jonathan Dumaresq
Jie Zhang
Evan
Jim Paris
Andreas Bießmann
olivier Schonken
Gunnar Henne
Spencer Oliver
SimonQian