With CLIC extension (smclic), mcause and mstatus CSRs
share mirrored fields for mpp and mpie. Therefore, neither
can be assumed cachable.
Signed-off-by: Samuel Obuch <samuel.obuch@espressif.com>
* Register file examination is separated.
* Allow to access registers through cache as early as possible to re-use
general register access interface and propely track state of the
register.
* Reduces the number of operations: S0 and S1 are saved/restored only
when needed (targets without abstract CSR access).
Change-Id: I2e205ae4e88733a5c792f8a35cf30325c68d96b2
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit creates file structure for register cache related
functions.
Specifically:
* `riscv_reg.h` -- general interface to registers. Safe to use after
register cache initialization is successful.
* `riscv_reg_impl.h` -- helper functions to use while implementing
register cache initialization.
* `riscv_reg.c` -- definitions of functions from `riscv_reg.h` and
`riscv_reg_impl.h`.
* `riscv-011_reg.h` -- register cache interface specific to 0.11
targets.
* `riscv-013_reg.h` -- register cache interface specific to 0.13+
targets.
* `riscv-011/0.13.h` -- version-specific methods used to access
registers. Will be extended as needed once other functionality (not
related to register access) is separated (e.g. DM/DTM specific stuff).
Change-Id: I7918f78d0d79b97188c5703efd0296660e529f2a
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Samuel Obuch
Evgeniy Naydanov