Commit Graph

9309 Commits

Author SHA1 Message Date
oharboe bb5f713e44 Gary Carlson <gcarlson@carlson-minot.com> config file
git-svn-id: svn://svn.berlios.de/openocd/trunk@2657 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-31 09:06:01 +00:00
oharboe 0dd669f2a7 Ferdinand Postema <ferdinand@postema.eu> config script for the MMnet1001 module from Propox.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2656 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-31 06:02:01 +00:00
oharboe 2a86a53c3f David Brownell <david-b@pacbell.net> Minor code bugfix: check right variable.
Via code review by Steve Grubb <sgrubb@redhat.com> 

Almost innocuous; this is value is checked later, this
check being wrong would make it check stack garbage.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2655 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 21:12:50 +00:00
oharboe 072d6d3db6 Dirk Behme <dirk.behme@googlemail.com> Fix typo in help text. It has to be 'production_test' instead of 'production' here.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2654 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 20:08:07 +00:00
oharboe fbe1c23c12 David Brownell <david-b@pacbell.net> Fix Sandstorm revision checking: right bits, right value!
git-svn-id: svn://svn.berlios.de/openocd/trunk@2653 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 20:05:40 +00:00
oharboe 98ae6c24f0 David Brownell <david-b@pacbell.net> Remove duplicate check for flash write status.
Via code review by Steve Grubb <sgrubb@redhat.com> 

Also minor fixes for the message from "fill":  the byte
count is unsigned, not signed; and more importantly,
print the real number of bytes written

git-svn-id: svn://svn.berlios.de/openocd/trunk@2652 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 20:04:17 +00:00
oharboe ab30d5203c David Brownell <david-b@pacbell.net> Minor doc updates:
- Itemize the list of private customization examples
  for openocd.cfg

 - Add "override defaults" as a customization, specifically
  for the work area (back it up or relocate it)

 - Highlight some work area location issues

git-svn-id: svn://svn.berlios.de/openocd/trunk@2651 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 17:32:56 +00:00
oharboe d879faa3cb David Brownell <david-b@pacbell.net> start phasing out integers as target IDs
git-svn-id: svn://svn.berlios.de/openocd/trunk@2650 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 17:30:14 +00:00
oharboe 4b9bdd664a David Brownell <david-b@pacbell.net> Be sure the built-in search paths always go *after* ones provided
on the command line ... matching comment in add_default_dirs().

Without this it's impossible to use a private config file which
happens to have the same name as an installed one.  Say, because
you're bugfixing a private copy...

git-svn-id: svn://svn.berlios.de/openocd/trunk@2649 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 17:27:50 +00:00
oharboe 69b8b5e0aa David Brownell <david-b@pacbell.net> fix warnings
git-svn-id: svn://svn.berlios.de/openocd/trunk@2648 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-28 17:18:36 +00:00
oharboe ed8fd94d7c added arm11 timeout error messages
git-svn-id: svn://svn.berlios.de/openocd/trunk@2647 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-28 13:43:26 +00:00
oharboe efef05870d restore ICE watchpoint registers when the *last* software breakpoint is removed
git-svn-id: svn://svn.berlios.de/openocd/trunk@2646 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-28 09:47:19 +00:00
oharboe a5d02116a6 David Brownell <david-b@pacbell.net> The Stellaris eval boards don't have TRST signals, so
defining ntrst_delay is pointless; don't.

At least the LM3S3748 eval board doesn't need nsrst_delay
either; remove that too.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2645 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-28 06:53:35 +00:00
oharboe 997d5284cb David Brownell <david-b@pacbell.net> ARM disassembly support for about five dozen non-Thumb instructions
that were added after ARMv5TE was defined:

 - ARMv5J "BXJ" (for Java/Jazelle)
 - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)

Compile-tested.  This might not set up the simulator right for the
ARMv6 single step support; only BXJ branches though, and docs to
support Jazelle branching are non-public (still, sigh).

ARMv6 instructions known to be mis-handled by this disassembler
include:  UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2

git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-28 06:52:08 +00:00
oharboe ae17ce23eb arm11 hardware step using simulation + breakpoint. Use "hardware_step enable" command to revert to hardware stepping. Ideally we could retire the "hardware_step enable" command once we no longer believe it to be necessary.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2643 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-27 10:37:01 +00:00
oharboe c5145ceb19 arm11 single stepping wip - at least we know the next PC now
git-svn-id: svn://svn.berlios.de/openocd/trunk@2642 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-27 07:37:07 +00:00
oharboe bb000a6f77 arm11 single stepping wip
git-svn-id: svn://svn.berlios.de/openocd/trunk@2641 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-27 07:35:47 +00:00
oharboe 32a2c70d3e refactor arm simulator to allow arm11 code to use it as well - no observable changes otherwise.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2640 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-27 06:50:36 +00:00
oharboe 641c574425 some arm11 stuff that isn't done yet.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2639 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:27:33 +00:00
oharboe 327ba6cb0a Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> cortex-a8: Wait for the CPU to be halted/started
With DCCR we are asking the CPU to halt, we should wait until
the CPU has halted before proceeding with the operation.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:25:44 +00:00
oharboe e921fead94 Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Print the value that the method didn't like
git-svn-id: svn://svn.berlios.de/openocd/trunk@2637 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:24:45 +00:00
oharboe 01000e988a Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Only dap_ap_select when we are going to do a memory access
in the fast reg case.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2636 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:23:35 +00:00
oharboe fc7cd1d85e Matt Hsu <matt@0xlab.org> cortex-a8: Copy some more registers from the documentation
git-svn-id: svn://svn.berlios.de/openocd/trunk@2635 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:22:28 +00:00
oharboe 56a04a3413 Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into
the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:21:26 +00:00
oharboe f36d0083de Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2633 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:20:25 +00:00
oharboe 56b346447b Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Before executing a new instruction wait for the previous
instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:16:08 +00:00
oharboe dce1cdc9fb David Brownell <david-b@pacbell.net> Fix segv in jtag_examine_chain(): exit loop on no-tap. Keep
"next iteration" step with the rest of the loop overhead.

Cleanup:  remove spurious whitespace, and an overlong line;
only assign "tap->hasidcode" once.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2631 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:06:56 +00:00
oharboe 0de530067f added missing check on jtag_execute
git-svn-id: svn://svn.berlios.de/openocd/trunk@2630 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 10:13:51 +00:00
oharboe c87357a33f Remove bogus "BUG:". If the PC is pointing to an invalid instruction, then simulation will fail. This is expected.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2629 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 10:03:54 +00:00
oharboe 9a9ebfb924 reduce arm11 output noise
git-svn-id: svn://svn.berlios.de/openocd/trunk@2628 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 08:32:03 +00:00
oharboe 11856bcffc Michael Schwingen <rincewind@discworld.dascon.de> news about xscale
git-svn-id: svn://svn.berlios.de/openocd/trunk@2627 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 07:11:16 +00:00
oharboe a5354ff5cb David Brownell <david-b@pacbell.net> Clock updates/fixes for the Stellaris flash driver:
- Bugfixes:
   * internal osc: it's *12* MHz (not 15 MHz) on _current_ chips
      + except new Tempest parts where it's 16 MHz (and calibrated!)
      + or some old Sandstorm ones, where 15 MHz was valid
   * crystal config:
      + read and use the crystal config, don't assume 6 MHz
      + know when that field is 4 bits vs 5
   * an RCC2 register may be overriding the original RCC
      + more clock source options
      + bigger dividers
      + fractional dividers on Tempest (NYET handled)
   * there's a 30 KHz osc on newer chips (for deep sleep)
   * there's a 32768 Hz osc on newer chips (for hibernation)

 - Cosmetic
   * say "rev A0" not "vA.0", to match vendor docs
   * don't always report master clock as an "estimate":
      + give the error bound if it's approximate, like "±30%"
      + else don't say anything
   * fix whitespace and caps in some messages
   * these are not AT91SAM chips!!

Those clock issues might explain problems sometimes reported when
writing to Stellaris flash banks; they affect write timings.

That 12-vs-15 MHz issue is problematic; there's no consolidated doc
showing which chips (and revs!) have which internal oscillator speed.
It's clear that only older silicon had the faster-and-less-accurate
flavor.  What's less clear is which chips are "old" like that.

Lightly tested, on a DustDevil part.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2626 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 06:26:29 +00:00
oharboe 34e8c67b1f David Brownell <david-b@pacbell.net> Various updates to 0.3.0 NEWS
git-svn-id: svn://svn.berlios.de/openocd/trunk@2625 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 20:03:35 +00:00
oharboe bc075606b7 David Brownell <david-b@pacbell.net> Tweak disassembly commands:
For ARMv4/ARMv5:
  - better command parameter error checking
  - don't require an instruction count; default to one
  - recognize thumb function addresses
  - make function static
  - shorten some too-long lines
 For Cortex-M3:
  - don't require an instruction count; default to one

With the relevant doc updates.
---
Nyet done:  invoke the thumb2 disassembler on v4/v5,
to better handle branch instructions.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 20:02:19 +00:00
oharboe 24f011ebb4 David Brownell <david-b@pacbell.net> More jtag_add_reset() cleanup:
Unify the handling of the req_srst parameter, and rip out a
large NOP branch and its associated FIXME.  (There didn't seem
to be anything that needs fixing; but that was unclear since
the constraints were scattered all over the place not unified.)

git-svn-id: svn://svn.berlios.de/openocd/trunk@2623 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 19:59:55 +00:00
oharboe 86b49612a6 David Brownell <david-b@pacbell.net> More jtag_add_reset() cleanup:
Unify the handling of the req_tlr_or_trst parameter.  Basically,
JTAG TMS+TCK ops ("TLR") is always used ... unless TRST is a safe
option in this system configuration.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2622 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 19:58:06 +00:00
oharboe 6f359fba68 David Brownell <david-b@pacbell.net> Some jtag_add_reset() cleanup:
- Track whether TRST and/or SRST actually change:

    * If they're not changing, don't ask the JTAG adapter to do anything!
      (JTAG TCK/TMS ops might still be used to enter TAP_RESET though.)
    * Don't change their recorded values until after the adapter says it
      did so ... so fault paths can't leave corrupt state.
    * Detect and report jtag_execute_queue() failure mode
    * Only emit messages saying what really changed; this includes adding
      an omitted "deasserted TRST" message.
    * Only apply delays after deasserting SRST/TRST if we *DID* deassert!

 - Messages say "TLR" not "RESET", to be less confusing; there are many
   kinds of reset.  (Though "TLR" isn't quite ideal either, since it's
   the name of the TAP state being entered by TMS+TCK or TRST; it's at
   least non-ambiguous in context.)

So the main effect is to do only the work this routine was told to do;
and to have debug messaging make more sense.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2621 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 19:55:32 +00:00
oharboe bd7cbd01e8 David Brownell <david-b@pacbell.net> Accomodate targets which don't support various target-specific
reset operations.  Maybe they can't; or it's a "not yet" thing.

Note that the assert/deassert operations can't yet trigger for
OMAP3 because resets currently include JTAG reset in all cases,
resetting the ICEpick and thus disabling the TAP for Cortex-A8.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2620 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 19:52:02 +00:00
oharboe 0c41395fc3 Michael Schwingen <rincewind@discworld.dascon.de> fix previous doc patch
git-svn-id: svn://svn.berlios.de/openocd/trunk@2619 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 13:00:45 +00:00
ntfreak 7a1ac49ac9 - fix build warnings
- add svn props to recently added files armv7a.[ch]

git-svn-id: svn://svn.berlios.de/openocd/trunk@2618 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 12:19:44 +00:00
oharboe 8e1d516927 Michael Schwingen <rincewind@discworld.dascon.de> a small CFI cleanup
git-svn-id: svn://svn.berlios.de/openocd/trunk@2617 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 08:21:11 +00:00
oharboe 696ed5fdc4 strange.... the code build and links w/Linux GCC target but fails w/arm-elf. The code was clearly broken as it was missing two extern's in the .h file...
git-svn-id: svn://svn.berlios.de/openocd/trunk@2616 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 07:17:19 +00:00
oharboe d11c8e3c8e Ferdinand Postema <ferdinand@postema.eu> fix warnings
git-svn-id: svn://svn.berlios.de/openocd/trunk@2615 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 07:14:05 +00:00
oharboe 14f2189e1a Ferdinand Postema <ferdinand@postema.eu> increase reset delay to fix regression from 2600 to 2604
git-svn-id: svn://svn.berlios.de/openocd/trunk@2614 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 07:12:57 +00:00
oharboe fd4c0f33b1 Michael Schwingen <rincewind@discworld.dascon.de> The attached patch adds a "xscale vector_table" command that allows to set
the values that are written in the mini-IC (plus documentation updates that
describe why this is needed).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2613 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 07:09:48 +00:00
oharboe ae4c224459 Audrius Urmanavičius <didele.deze@gmail.com> Latest source (R2606) does not compile under Windows+Cygwin - fails with error about possibly uninitialized use of variable 'ch'.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2612 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 07:04:25 +00:00
oharboe 41bb41bb93 Brian Findlay <findlaybrian@gmail.com> finalize mini2440.cfg
git-svn-id: svn://svn.berlios.de/openocd/trunk@2611 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 07:02:50 +00:00
oharboe 9df861b0c0 use cortex_a8 instead of cortex_m3
git-svn-id: svn://svn.berlios.de/openocd/trunk@2610 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 06:59:42 +00:00
oharboe 1d0b276c9f David Brownell The rest of the Cortex-A8 support from Magnus: replace the previous
nonfunctional cortex_a8 code with something that at least basically
works (for halt/step/resume, without MMU) even if it is incomplete.
(With tweaks from Øyvind, and cleanup from Dave.)

This code has mainly been developed and tested against R1606, it has 
been built and tested against R2294 where it runs but step and resume 
commands are broken due to regression (which should be fixed now).

This code is really written for OMAP3530.  It doesn't identify debug
resources using generic DAP calls to scan the ROM table, or perform
topology detection.  The OMAP3530 DAP exposes two memory access ports:

 - Port #0 is connected to L3 interconnect (the main bus) with
   passthrough to the L4 EMU bus ... so it will be used for most
   memory accesses.

 - Port #1 is connected to a dedicated debug bus (L4 EMU), with
   access to L4 Wakeup, and holds the ROM table ... so it must
   be used for most debug and control operations.

The are some defines to handle this in cortex_a8.c, which should be
replaced with more general code.  Having access to another Cortex-A8
implementation would help get that right.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2609 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 06:58:34 +00:00
oharboe 6f7491c1c1 David Brownell Subset of Cortex-A8 support from Magnus: create an armv7a file
and seed it with DAP access support using the current ADIv5 code.
(With tweaks and cleanup from Øyvind and Dave.)

The ARMv7-AR architecture manual is not publicly available (even
in subset form like the ARMv7-M spec), so it's hard to distinguish
between the Cortex-A8 implementation and the ARMv7-A architecture.

The register set presumably is architectural, and so it's stored
here; it's like earlier ARMs, with small additions.  Ditto the
instruction set, though Thumb2 support is used (extending Thumb
support from ARMv6 with more 32-bit instructions) and there's this
ThumbEE thing too.  There is a new "debug monitor" mode, not yet
fully addressed here, to support debugging in environments (like
motor control) where halting debug mode is inadvisable.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2608 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-25 06:57:26 +00:00