Commit Graph

7660 Commits

Author SHA1 Message Date
Matthias Welwarsky 8b140fd724 cortex_a: replace cortex_a_check_address function
When accessing memory through the ARM core, privilege levels and mmu
access permissions observed. Thus it depends on the current mode of the
ARM core whether an access is possible or not. the ARM in USR mode can
not access memory mapped to a higher privilege level. This means, if the
ARM core is halted while executing at PL0, the debugger would be
prevented from setting a breakpoint at an address with a higher privilege
level, e.g. in the OS kernel. This is not desirable.

cortex_a_check_address() tried to work around this by predicting if an
access would fail and switched the ARM core to SVC mode. However, the
prediction was based on hardcoded address ranges and only worked for
Linux and a 3G/1G user/kernel space split.

This patch changes the policy to always switch to SVC mode for memory
accesses. It introduces two functions cortex_a_prep_memaccess() and
cortex_a_post_memaccess() which bracket memory reads and writes. These
function encapsulate all actions necessary for preparation and cleanup.

Change-Id: I4ccdb5fd17eadeb2b66ae28caaf0ccd2d014eaa9
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3119
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 10:07:54 +00:00
Matthias Welwarsky 3683f8cef0 cortex_a: rework mmu manipulation
when disabling the mmu to access physical addresses, normally the d-cache
must be disabled as well. Disabling the d-cache also requires a full
clean&invalidate. However, since all memory writes are treated as write-
through no-allocate and memory reads do not allocate cache lines,
effectively the d-cache state does not change at all. We can therefore
save the the d-cache disabling and flushing.

This patch also simplifies the function a bit.

Change-Id: Ia17c56a28f432156429cd4596107e3652b788e63
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3114
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30 10:07:33 +00:00
Matthias Welwarsky 442e2506b1 cortex_a: force cache and tlb bypass when cpu is in debug state
for minimal impact on the hardware state, force all memory accesses to
bypass the caches and tlbs. This may actually be the default, but ARM
recommends in DDI0406C to set proper default values on debug init.

Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3079
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 10:07:10 +00:00
Matthias Welwarsky 6d7f5be6ac armv7a: fix-up dcache clean and flush functions inner loop pattern
Other cache functions use an updated pattern for the address range loop.
Bring dcache clean and flush functions in line.

Change-Id: Iccb4a05c49054471033a3403363110cb08245d5b
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3035
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30 05:43:42 +00:00
Matthias Welwarsky f24aa404ba cortex_a: Update instruction cache after setting a soft breakpoint
Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint,
to make sure the d-cache is clean and invalid at the breakpoint
location down to PoC.

Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint
again, so that d-cache will pick up the modified code.
Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint
to memory to make the change visible to the CPU.

Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3033
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 05:43:03 +00:00
Matthias Welwarsky 9484dd5ebf armv7a: correctly handle invalidation of inner data caches
D-Cache invalidate is a dangerous operation. It will only work correctly
if full cache lines are invalidated. When partial cache lines are
invalidated, i.e. the target address range does not start and end
at a cache line boundary, cpu data writes outside of the target range
will be dropped. This patch adds special treatment for partial cache
lines by doing a clean & invalidate on the partial lines before
invalidating the rest of the range.

Change-Id: I64099ddb058638e990a7eb0ee911b9cc8f6f8901
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3034
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30 05:42:35 +00:00
Matthias Welwarsky f3716894c6 armv7a: fix debug messages regarding cache on/off state
Cache bits are not level specific, remove "l1" from debug message.
Also, fix data/instruction mixup in armv7a_l1_i_cache_sanity_check()

Change-Id: I259665ffe62c7ada5b4f98d3fd907e93662d4091
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3028
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 05:42:13 +00:00
Matthias Welwarsky d17c11759f armv7a: rework automatic flush-on-write handling
The following changes are implemented:
- Clean&Invalidate the VA range to PoC *before* the write takes place
- Remove SMP handling since DCCIMVA instruction already maintains SMP
  coherence.
- Remove separate Invalidate step

Change-Id: I19fd3cc226d8ecf2937276fc63258b6a26e369a7
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3027
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 05:41:58 +00:00
Matthias Welwarsky 7986faba21 armv7a: add d-cache virtual address range flush function
This patch adds a function for cleaning & invalidating a virtual
address range from the architecture caches down to the point of
coherence.

Change-Id: I4061ab023a3797fabc967f3a34498034841d52c6
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3026
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 05:41:35 +00:00
Matthias Welwarsky cd1a345267 armv7a: remove indirection for cache info handler
There's only one function left that handles cache info display,
no need any more for a function pointer and runtime initialization.

Change-Id: I90b09577f81607917b11f0ab5600a0e2dce223e2
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3025
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 05:41:16 +00:00
Matthias Welwarsky 8704e53665 armv7a: fix handling of inner caches
ARMv7 architecture allows up to 7 cache levels that are architecturally
visible, as opposed to "system caches", which are outside of the domain
defined by ARMv7 and require separate management. This patch enables
detection and identification of caches at all levels. It also implements
a new "flush-all" function that cleans & invalidates all cache levels to
the "Point of Coherence".

Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3024
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 05:40:57 +00:00
Matthias Welwarsky 3a292a1f34 armv7a: remove special l2x flush-all and cache-info handlers
This patch is on the path to unified handlers for both inner and
outer caches. It removes the special overrides installed when
an outer cache is configured.

Change-Id: I747f2762c6c8c76c700341cbf6cf500ff2a51476
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3022
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30 05:40:34 +00:00
Matthias Welwarsky 4ba83e1c9b armv7a: rename l2_cache to outer_cache
The outer cache is not necessarily at L2 in a system. Rename functions
to make that clear.

Change-Id: Ia636a4844f50634f2bdf5cdce285febc1a47c11f
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3020
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30 05:40:05 +00:00
Oleksij Rempel 0df5577282 armv7a: remove l1 flush all data handler
deprecated by new code.

Change-Id: Ie3db627803a6aae38a5287bd3a748a78ab084b7d
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2801
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30 05:39:50 +00:00
Oleksij Rempel cd440bd32a add armv7a_cache handlers
This patch introduces, new command set and handlers for l1 and l2x caches.

Patch set 10 folded the following changes into this one:

Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415
If8d87a03281d0f4ad402909998e7834eb4837e79
I0749f129fa74e04f4e9c20d143a744f09ef750d8

Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/2800
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30 05:39:40 +00:00
Oleksij Rempel 74592a8435 cortex_a: add cortex_a_[read|write]_memory_ahb
Change-Id: I39c457274e1714a8d42233f7fc490fb58f5cb38e
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2798
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 05:39:15 +00:00
Oleksij Rempel 2f3127e1ab cortex_a: add cortex_a_[read|write]_buffer
Change-Id: I82011822d913aa7228f5c6262b540156494bedfe
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2797
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 05:38:54 +00:00
Oleksij Rempel b55361d07f cortex_a: remove cache handlers from cortex_a_write_phys_memory
This was needed for ahb access

Change-Id: I638f45a276a593c08140b5d9d7480617aa85f096
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2796
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
2015-11-30 05:38:24 +00:00
Oleksij Rempel f478107d02 cortex_a: remove ahb support for phys_memory access
Change-Id: I5b7c21c16e95cc1a3160e356d6e64f1f8c449e6e
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2795
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30 05:37:56 +00:00
Alamy Liu bfba15a898 adi_v5: Fix wrong ap value
Problem
dap->ap_current is register value, not field value.
it restores invalid ap when it calls dap_ap_select(dap, ap_old) later.

* assume the current ap is 1, dap->ap_current value would be (1 << 24).
ap_old = dap->ap_current;   <-- ap_old = 1<<24 = 0x1000000.
...
dap_ap_select(dap, ap_old); <-- select 0x1000000, not 1.
* All AP registers accessing fail afterwards.

One of the reproducible case(s): CORE residents in AP >= 1
  dap_lookup_cs_component() being used to find PE(*).
  In most cases, PE would be found in AP==0, hence the problem is hidden.
  When AP number is 1, dap->ap_current would have the value of 1<<24.
  Anyone get the AP value with dap->ap_current and resotre it later would
  select the wrong AP and all accessing later would fail.

  The ARM Versatile and/or FPGA would have better chance to provide this
  kind of environment that PE residents in AP>=1. As they have an 'umbrella'
  system at AP0, and main system at AP>=1.

  * PE: Processing Element. AKA Core. See ARM Glossary at
    http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014g/ABCDEFGH.html

Fix
Use dap_ap_get_select() to get ap value.
a. Retrieve current ap value by calling dap_ap_get_select();
     src/flash/nor/kinetis.c
     src/target/arm_adi_v5.c

b. The code is correct (dap->ap_current >> 24), but it's better to use
   dap_ap_get_select() so everything could be synchronized.
     src/flash/nor/sim3x.c

Change-Id: I97b5a13a3fc5506cf287e299c6c35699374de74f
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2935
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-11-27 10:38:22 +00:00
Marc Schink 4b608d7fea jlink: Retrieve maximum speed from device.
If supported, the maximum transport speed is now retrieved from the
device.

Change-Id: I614f405ec91cf199c851781785fd26cbd10c37a6
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2955
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-26 12:21:30 +00:00
Marc Schink 442f1540d5 Improve J-Link driver and introduce libjaylink.
This patch uses libjaylink which is a library to access J-Link
devices. As other tools which are not in the scope of OpenOCD also
need to access J-Link devices a library is used. A firmware upgrade
tool and an advanced configuration tool for J-Link devices are under
development.

Further versions of libjaylink will support additional features
OpenOCD could benefit from. This includes TCP/IP as additional
possibility to connect to J-Link devices as well as power tracing and
device internal communication. The latter is used to access
peripherals on some development boards (e.g EFM32 STK and DVK).

Integration of libjaylink is realized with a git submodule like
jimtcl. As libjaylink depends on libusb-1.0 only, no additional
dependency is introduced for OpenOCD.

All low-level JTAG and SWD implementations of the current driver are
left untouched and therefore no incompabilities are to be expected.

Improvements of this patch:

 * Support for more USB Product IDs, including those with the new
   scheme (0x10xx). The corresponding udev rules are also updated.
 * Device selection with serial number and USB address.
 * Adaptive clocking is now correctly implemented and only usable for
   devices with the corresponding capability.
 * The target power supply can now be switched without the need for
   changing configuration and power cycling the device.
 * Device configuration is more restrictive and only allowed if the
   required capabilities are available.
 * Device configuration now shows the changes between the current
   configuration of the device and the values that will be applied.
 * Device configuration is verified after it is written to the device
   exactly as the vendor software does.
 * Connection registration is now handled properly and checks if the
   maximum number of connections on a device is reached. This is also
   necessary for devices which are attached via USB to OpenOCD as
   some device models also support connections on TCP/IP.
 * Serial Wire Output (SWO) can now be captured. This feature is not
   documented by SEGGER however it is completely supported by
   libjaylink.

This patch and libjaylink were tested on Ubuntu 14.04 (i386),
Debian 7 (amd64), FreeBSD 10.0 (amd64) and Windows XP SP3 (32-bit)
with the following device and target configurations:

 * JTAG: J-Link v8.0, v9.0 and v9.3 with AT91SAM7S256
 * SWD: SiLabs EFM32 STK 3700 (EFM32GG990F1024)
 * SWD: J-Link v8.0, v9.0 and v9.3 with EFM32GG990F1024
 * SWD: XMC 2Go (XMC1100)
 * SWD: XMC1100 Boot Kit (XMC1100)
 * SWD: IAR Systems / Olimex Eval Board (LPC1343F)
 * SWD: Nordic Semiconductor nRF51 Dongle (nRF51422)
 * SWD: SiLabs EZR32 WSTK 6220A (EZR32WG330FG60G)

Except for Windows XP all builds are tested with Clang in addition to
GCC. This patch and libjaylink are not tested on OSX yet.

Change-Id: I8476c57d37c6091c4b892b183da682c548ca1786
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2598
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-26 12:19:22 +00:00
Jakub Kubiak 9a6d6b51b7 flash/nor/lpc2000: add alternative part ID for LPC1343
http://support.code-red-tech.com/CodeRedWiki/DebugAccessChip
> Note that once you have recovered debug access to your MCU, then in most cases you should then modify your Debug Configuration to turn vector catch off again. If this is not done, then this can cause problems in some circumstances with some versions of the Code Red IDE. For example with NXP LPC13xx parts, connecting more than once to the MCU with vector catch enabled can lead to the part ID being incorrectly read - which can again cause debug connections to fail
This patch adds an alternative part ID for LPC1343. With this patch "program" command works fine for flashing.

Change-Id: I8632e898a4c33102455925d25715b4f4edfa1d97
Signed-off-by: Jakub Kubiak <jakub@kubiak.es>
Reviewed-on: http://openocd.zylin.com/2782
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-26 12:17:54 +00:00
Bogdan Kolbov ae2142d5a2 niietcm4: support for NIIET's Cortex-M4 microcontrollers
This adds docs, example config, flash driver.
Driver is only supports K1921VK01T model for now.

Change-Id: I135259bb055dd2df1a17de99f066e2b24eae1b0f
Signed-off-by: Bogdan Kolbov <kolbov@niiet.ru>
Reviewed-on: http://openocd.zylin.com/3011
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-26 12:17:25 +00:00
Karl Palsson 7a8915ff64 efm32: remove duplicate part name decoding.
The probe and info methods had duplicate sections decoding family names
to generate a human friendly part name.  Extract this to a common
helper.

Change-Id: I4c6309d83c601e154b7c14ad9c15c53854ee1e98
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/2932
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-23 16:08:25 +00:00
Karl Palsson 3f48732700 efm32: basic Happy Gecko target support
Basic basic support to get running, magic numbers taken from revision
0.90 of the reference manual.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Change-Id: Iff6ab94d30698f056ef09f7a856b7285fed8f441
Reviewed-on: http://openocd.zylin.com/2931
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-23 16:08:04 +00:00
Felipe Balbi 2bb9256c34 jtag: commands: save a pointer to list tail
By saving a pointer to the tail of the list,
we don't need to traverse the entire command
queue before we're able to append an item to
it.

With this patch, I see a 10% improvement when
using the embedded XDS100v2 on AM437x IDK board
to load a 4MiB binary (linux zImage) to DDR
with load_image.

IOW, we went from ~305kB/sec to ~336kb/sec.

Change-Id: Idb55d49f0d0106043374ab520b2f3b6b32f2c50f
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2709
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Daniele Emancipato <daniele12457@hotmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-23 15:54:11 +00:00
Paul Fertser a652a4ea20 svf: fix progress reporting switch behaviour
The svf_progress_enabled variable is global, hence its lifetime is not
limited and it retains the value from the previous run. Fix this by
explicit assignment.

Change-Id: Id6f4fa88f39521606342a37f6876a0948ac5406e
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3111
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-20 22:27:48 +00:00
Paul Fertser 40bd770f45 svf: fix off-by-one error in line numbers as output to user
This makes SVF error output match actual line numbers in the file
processed.

Change-Id: I1fa4b9d0891e4358b7beada516945d5331ebe182
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2945
Tested-by: jenkins
2015-11-20 22:26:21 +00:00
Tomas Vanek d028d84026 Kinetis: suppress false alarms "MCU is secured"
Kinetis driver checks MDM STAT register to detect secured state of MCU.
An unsecured clean device typically triggered a huge fat alarm message.
Now when driver detects secured state it tries to halt MCU and then
re-reads status register.

Command "mdm mass_erase" used to deassert reset when finished
and MCU started looping in hard fault - WDOG reset cycle.
Now "reset halt" is issued. Clean flash is not run after mass_erase.

Change-Id: I23f393509fbd8751d44ffc744ff2d67f1074f74e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3010
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-20 22:19:03 +00:00
Andreas Färber 2594c23d78 tcl/target: Add Nordic nRF52 config
Base config without flash support for now.

Change-Id: I96a5b6ad35e00dc706177ea9dbdffc384ae7f62b
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3110
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-20 18:28:40 +00:00
Jonathan Larmour 7f93aabd61 tcl/board: Remove pflash.0 bank from twr-k60n512.cfg
The pflash.0 bank should not be present as it overlaps with
the flash bank created by target/kx.cfg, triggering an error.
This is also in line with the existing twr-k60f120m.cfg.

Change-Id: I5f620e01319d967f12e029fb6865ccdd031713b3
Signed-off-by: Jonathan Larmour <jifl@eCosCentric.com>
Reviewed-on: http://openocd.zylin.com/3108
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2015-11-20 18:27:54 +00:00
Tomas Vanek 26a65f4f13 flash: at91samd: flash write code cleaning
SAMD driver suffered from following problems:

1) Flash was erased as an integral part of flash write.
It was not documented so with usual workflow it resulted
in erasing flash twice (and reducing flash lifespan)
and in almost double flashing time.

2) Sector erase was silently skipped if "is_erased" flag was set.
"is_erased" logic was not reliable, e.g. when a row write
was aborted after successful write of some pages, sector was
still considered as erased. "is_erased" flag could not
cope with flash writes from a user program.

3) Writing of a block with start address unaligned to a flash page
resulted in failed assert and OpenOCD abort.

4) Disabling cache in bit 18 of 16-bit halfword never worked.
MCU implements cache invalidate in hardware so there is no need
to take care about. This bug was reported by Tony DiCola.

New code does not erase flash in write operation.
Instead it traditionally relies on erasing flash beforehand.
"is_erased" logic and cache disabling is completely removed.
It simplifies write procedure a lot and flash write is now faster.

The change partly solves ticket #109 SAMD/SAM4L driver doubles flash erase.

Change-Id: I582b497d01a351575533a1f8c9810a4413be0216
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3045
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-20 18:26:58 +00:00
Andreas Loehre b5fa1e4d77 flash: at91samd: Add SAML21 variant B device support and fix SAMC20/SAMC21
This adds support for the Atmel SAML21 variant B parts.
There is minimal change between the two variants, but in
variant B the automatic page write which the at91samd flash
driver relies on to be enabled is disabled by default.
With this patch the write row function will now issue a page write
command after each of the four pages in the row if the MANW (manual
write) bit is set. This also fixes flash write for the SAMC20/SAMC21
devices which have the MANW bit set by default as well.

I have also moved the device ID (DID) register bitfield extraction
from the find_part into helper macros. These can be used in the future
if there are more workarounds for specific devices.

Tested (programming) on:
ATSAML21-XPRO
ATSAML21-XPRO-B
SAMC21 Xplained Pro
SAMD21 Xplained Pro
SAMD20 Xplained Pro

Change-Id: I401a8aa1efd64730840c0d62cf49a1e880ea5900
Signed-off-by: Andreas Loehre <alohre@gmail.com>
Reviewed-on: http://openocd.zylin.com/2903
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2015-11-20 18:26:47 +00:00
Tomas Vanek 72c3464be4 jtag: cmsis-dap: Issue disconnect before reconnecting
cmsis-dap protocol has both DAP_Connect and DAP_Disconnect commands.
Logically if cmsis_dap_swd_switch_seq() calls DAP_Connect in connected
state it should call DAP_Disconnect first.

Doing so surprisingly solves problems on Atmel EDBG with target SAMD/R/L/C.
Without this change SWD communication breaks after reset run/halt
in config "reset_config srst_only" and reconnect trials repeatedly
fail with "SWD ack not OK: 0 JUNK"

Change-Id: Ie951098d5e0c83f388e2df414608aaabec2135c9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3098
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-20 18:26:12 +00:00
Tomas Vanek 751e2454bf at91samd: handle reset run/halt in DSU
Atmel introduced a "Device Service Unit" (DSU) that holds the CPU
in reset if TCK is low when srst (RESET_N) is deasserted.
Function is similar to SMAP in ATSAM4L, see http://openocd.zylin.com/2604

Atmel's EDBG adapter handles DSU reset correctly without this change.

An ordinary SWD adapter leaves TCK in its default state, low.
So without this change any use of sysresetreq or srst
locks the chip in reset state until power is cycled.

A new function dsu_reset_deassert is called as reset-deassert-post event handler.
It optionally prepares reset vector catch and DSU reset is released then.

Additionally SWD clock comment is fixed in at91samdXX.cfg and clock is
lowered a bit to ensure a margin for RC oscillator frequency deviation.
adapter_nsrst_delay 100 is commented out because is no more necessary after
http://openocd.zylin.com/2601

Change-Id: I42e99b1b245f766616c0a0d939f60612c29bd16c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2778
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-20 18:26:05 +00:00
Paul Fertser 64802b7939 tcl/interface/ftdi: add 100ask's OpenJTAG config
Schematics provided by Matthias Bock.

Change-Id: I3d00453fece3b4df58a53bee21fff646a8b71a34
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2718
Tested-by: jenkins
2015-11-16 16:17:18 +00:00
Felipe Balbi e4848fe043 board: ti_am437x_idk: default to 1000kHz
16000kHz is only safe after PLLs have been locked
properly. Until that's done (with reset init), we
can only safely run at 1000kHz.

Change-Id: I4e0a17e88aa9919cd6c34d44da68e23115c0d3a3
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/3015
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-13 06:59:12 +00:00
Ragnar Sundblad dd70e57b82 topic: Interface config file for FTDI UM232H module
Added interface config file for the FTDI FT232H based UM232H module.
This should work with UM232H-B too, an even cheaper module, but
that has not been tested.

Change-Id: Ifc312d6741da0b7862fe07d854023190d7afe251
Signed-off-by: Ragnar Sundblad <raggesu@gmail.com>
Reviewed-on: http://openocd.zylin.com/3031
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-13 06:57:58 +00:00
Paul Fertser 60d5701590 target: cortex_a: add deinit_target handler to free memory
Tested with Valgrind accesing a Pandaboard.

Change-Id: I51bba044974ecfc4d418998816d44a8563264123
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3101
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-13 06:55:26 +00:00
Uwe Bonnes f3be0f6071 stm32l4: Add cpu and stm32l4discovery board configuration.
Change-Id: I20d3fcee04516eb3b9bb22933e7e366eed0c0b2e
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2942
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-12 20:21:06 +00:00
Uwe Bonnes 6b32fe4124 tcl: Add default hooks for STM32F0x
Keep clocks running in low power modes. Stop watchdogs from interfering
with the debug session. Set up PLL and increase clock at reset init.

Change-Id: I232d769d893d54e4ea9411c46c56b19587b69919
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2707
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-12 20:20:33 +00:00
Uwe Bonnes d8ac9d5ac5 tcl: Add default hooks for STM32F4x
Set up PLL and increase clock at reset init.

Change-Id: I611bc6fb7c0c5afd8ed3f4ad8e64f3c7b981d31c
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2609
Tested-by: jenkins
Reviewed-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-12 15:24:19 +00:00
Uwe Bonnes c4b8c74140 stm32xxx.cfg: Only touch IWDG and WWDG in DBGMCU_APB1_FZ.
Change-Id: Ie0298c8e73bebeccc9346534d63aab4cae49e4f7
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3104
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-12 15:03:40 +00:00
Rémi PRUD’HOMME c3ea15dc62 Add config files for STM32F7-DISCO and STM327[4|5]6G-EVAL.
Change-Id: I0803939f0ab1de97e544ca0f1257daac11fb50de
Signed-off-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com>
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2754
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-12 15:03:18 +00:00
Andreas Färber ed54838ea6 flash/nor/xmc4xxx: Loosen checks for XMC4500
According to Infineon, XMC4500 EES AA13 with date codes before GE212 -
as seen on an XMC4500 General App Kit - had a zero SCU_IDCHIP register.

Handle this by extending our checks to not error out on zero SCU_IDCHIP
and by printing a useful info string in that case.

Change-Id: Ic2d641a314627dd5a1ff775a0113999191b95e3d
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2751
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
2015-11-11 12:10:48 +00:00
Jeff Ciesielski 33b048d456 flash: New driver for XMC4xxx microcontroller family
This is a complete flash driver for the Infineon XMC4xxx family of
microcontrollers, based on the TMS570 driver by Andrey Yurovsky.
The driver attempts to discover the particular variant of MCU via a
combination of the SCU register (to determine if this is indeed an
XMC4xxx part) and the FLASH0_ID register (to determine the variant).
If this fails, the driver will not load.
The driver has been added to the README and documentation.

Tests:
* Hardware: XMC4500 (XMC4500_relax), XMC4200 (XMC4200 enterprise)
* SWD + JTAG
* Binary: 144k, 1M

Note:
* Flash protect only partly tested. These parts only allow the flash
  protection registers (UCB) to be written 4 times total, and my devkits
  have run out of uses (more on the way)

Future Work:
* User 1/2(permalock) locking support via custom command
* In-memory flash loader bootstrap (flashing is rather slow...)

Change-Id: I1d3345d5255d8de8dc4175cf987eb4a037a8cf7f
Signed-off-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2488
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-11 12:08:35 +00:00
Morgan Quigley 42c24acebd flash: driver for Atmel SAMV, SAMS, and SAME
This is a driver for the Atmel Cortex-M7 SAMV, SAMS, and SAME.
I started with the at91sam4.c driver and then restructured it
significantly to try to simplify it and limit the functionality
to just a flash driver, as well as to comply with the style guide.

Change-Id: I5340bf61f067265b8ebabd3adad45be45324b707
Signed-off-by: Morgan Quigley <morgan@osrfoundation.org>
Reviewed-on: http://openocd.zylin.com/2952
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2015-11-10 20:27:09 +00:00
Morgan Quigley d85207c8e5 tcl/board: add Atmel SAM V71 Xplained Ultra
Tested with cmsis-dap using the EDBG chip on the board.

Change-Id: I3d398685c81e4701a9f6c1a66e60f7a87f839daa
Signed-off-by: Morgan Quigley <morgan@osrfoundation.org>
Reviewed-on: http://openocd.zylin.com/3092
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-10 20:27:00 +00:00
Morgan Quigley bdd0440508 tcl/target: add config for Atmel SAMV / SAMS / SAME
Change-Id: Ia90a533fe3d07f9a67ce2da815146c612d80dd1b
Signed-off-by: Morgan Quigley <morgan@osrfoundation.org>
Reviewed-on: http://openocd.zylin.com/3091
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2015-11-10 20:26:29 +00:00