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3 Commits

Author SHA1 Message Date
Olivier DANET 4e872a797f target/zynqmp : Add AXI AP access port 
The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs.

Change-Id: I6303331c217795657575de4759444938e775dee1
Signed-off-by: Olivier DANET <odanet@caramail.com>
Reviewed-on: http://openocd.zylin.com/6263
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
 2021-05-22 10:12:01 +01:00
Antonio Borneo 360b2c2701 tcl: replace '-ctibase' with '-baseaddr' 
Replace the deprecated option '-ctibase' with the generic option
'-baseaddr'.

Change generated with command:
	sed -i 's/-ctibase/-baseaddr/g' $(find tcl/ -type f)

Change-Id: If776934d2ac106532708768bb3a4ec6fcffb0368
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5870
Tested-by: jenkins
 2020-11-04 17:37:36 +00:00
Jonathan McDowell d2fb461621 Correct ZynqMP configuration to be appropriately named 
The xilinx_ultrascale.cfg target is actually the configuration for a
ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad
core A53. Update the filename/comments to reflect this, and include
the tap IDs for all known FPGA cores for this part.

Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4850
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
 2019-01-23 15:26:48 +00:00