Commit Graph

7687 Commits

Author SHA1 Message Date
Matthias Welwarsky 6fb9f2e3ee armv8: factor out generic bit set/clr for debug registers
introduce armv8_set_dbgreg_bits() function to make register 
bit-field modifications easier to read.


Change-Id: I6b06f66262587fd301d848c9e0645e8327653de7
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3989
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24 09:15:18 +00:00
Matthias Welwarsky 095ff3d210 armv8: load aarch32 register through aarch64 equivalent
The aarch32 register cache is only a separate view of the aarch64
registers. Load aarch32 registers through their aarch64 equivalents.

Change-Id: I3e932dfb782f03d73d30d942b24db340a5749e47
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3988
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24 09:14:59 +00:00
Matthias Welwarsky 8b923532c1 aarch64: remove bogus address check before memory access
Mmu faults can not be prevented on aarch64, they need to be taken and
handled accordingly. Remove the remaining stub code.

Change-Id: I6241efa594fe6b963624f9628cdf1c8e46588223
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3987
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24 09:14:32 +00:00
Matthias Welwarsky 9527d1e595 target: generic ARM CTI function wrapper
Not specific to ARMv8, the Cross Trigger Interface
deserves an independent access wrapper.

Change-Id: I84f8faad15ed3515e0fff7f6cc5d1109ef91a869
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3986
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24 09:13:52 +00:00
Matthias Welwarsky 7ed0b6333d aarch64: optimize core state detection
Replace loop by right-shift.
Inspired by patch from Alamy Liu

Change-Id: I1285f4f54c0695a93fa42e9863ed8ffa4de00f70
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3985
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24 09:13:10 +00:00
Matthias Welwarsky fa8700cdd5 aarch64: reduce debug output to improve legibility
Suppress some very verbose LOG_DEBUG's that are not really useful
any more.

Change-Id: I67f10ba9510a9e34a027f378f4b62b8901ddc8a4
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3984
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24 09:12:53 +00:00
Matthias Welwarsky 06ba5492df aarch64: remove mrs/msr functions from struct arm
No longer needed, no users.

Change-Id: I0cc82a0ef11e1b72101fa9145f014e5d5d76df0e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3983
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24 09:12:37 +00:00
Matthias Welwarsky f988f59604 aarch64: refactor SCTLR manipulation
Reduce SLOCs in SCTLR retrieval and modification functions and make them
less complex.

Change-Id: Ida1a99c223743247f171b52eef80dc9886802101
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3982
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24 09:12:23 +00:00
Matthias Welwarsky 5d00fd9d1d aarch64: fix software breakpoints when in aarch32 state
Use the correct opcode for Aarch32 state, both for the breakpoint
instruction itself and the cache handling functions.

Change-Id: I975fa67b1e577b54f5c672a01d516419c6a614b2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3981
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24 09:11:52 +00:00
Tim Newsome 3bd661b679 Speed things up by ignoring return values.
The remote bitbang implementation is really slow when reading back data.
During many operations, like writing a block of memory, we don't need to
see the return data. By communicating this to the lower layers, we get
huge speedups. Downloads to spike now are 295KB/s.

That means the gdbserver.py download test now runs to completion,
unfortunately it fails. Everything else is still passing, though, so I'm
committing this change.

Change-Id: I44cc9db1ade0908c1a12d09b23fc8e529a802d88
2017-02-22 16:04:36 -08:00
Tim Newsome f9168b09d0 Optimize memory write code, used in download.
To spike now we download at 5KB/s. But in real hardware performance
should be pretty OK now.

Change-Id: Ie6086cf156c9a00ac55400870346e27b28e3c755
2017-02-21 20:31:50 -08:00
Tim Newsome 4e8cf4aeb5 Better error checking in memory access.
Change-Id: I985afa433a09f833137f2e244b7eaad2630f6b1a
2017-02-20 17:53:18 -08:00
Tim Newsome aba0c0973d Properly restore s0 and s1 on resume.
Now 33/39 of the gdbserver tests pass!

Change-Id: I0cb38fbbcdc2c037ff0ec77229e79f24fa021663
2017-02-20 15:47:31 -08:00
Tim Newsome 3173314f28 Fix access FPU registers again.
Not a great fix. There's still a problem with accessing 64-bit floating
point registers on 32-bit cores.
24 of the gdbserver.py tests pass now.

Change-Id: I69a88ef5fd5581e2c7bf1d78057fd474ae86ff93
2017-02-17 19:03:32 -08:00
Tim Newsome 071f9a2916 Fix use of REG vs CSR constants.
23 gdbserver.py tests pass now.

Change-Id: I32805d615ae5f536f179baf906e0e74a56e80c0b
2017-02-17 12:35:43 -08:00
Tim Newsome b363d1a37e Bunch of register access refactoring.
Got rid of the last reference to the old debug RAM code! (Mostly?)
SimpleF18Test passes now.

Change-Id: Iab51d436a50bec9a5e504df7fb3cd6be874da0be
2017-02-17 11:53:37 -08:00
Tim Newsome 88f14f4d5e Check busy before triggering another command.
This version was able to download code, and run to a breakpoint.

Change-Id: I0ead8350579263d8e55f8df35e2b7af6c374ef21
2017-02-16 14:21:17 -08:00
Tim Newsome ef3875a320 Check for errors after read/write.
The code doesn't do anything intelligent if errors are found.
But MemTestBlock now also passes. I'm not quite sure why.

Change-Id: I8512f0a96db9e34d3db6a4a9bcef6e56f191d4c1
2017-02-15 20:41:39 -08:00
Tim Newsome 035b4dd17a Fix double read, which might have side effects.
Now passing MemTest{8,16,32,64}

Change-Id: I286d1e2a388d41853e5aa9049490ddb6135b61f1
2017-02-15 19:05:51 -08:00
Tim Newsome 713c001242 Make MemTest32 pass.
Change-Id: I9be90b07be695c976380f9fd50b971f8bb94f513
2017-02-15 17:10:53 -08:00
Tim Newsome 79e840aaa7 Some memory access works.
MemTest16 passes, but MemTest32 fails.

Change-Id: I17fbc38b4228b27c7fb3dadb15e9c1a2f67bcd65
2017-02-15 15:44:36 -08:00
Marc Schink 7c85165bc1 aarch64: Fix #include guards
Change-Id: I9445b04a210dcde5f8a7cf1560ef23eb53149178
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3975
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-15 12:48:18 +00:00
Tim Newsome 657e844c8c Merge pull request #15 from sifive/get_set_reg_error
Use the set/reg register error return code when registers don't exist.
2017-02-14 17:28:10 -08:00
Tim Newsome ceb8dc048d Make general CSR reads work.
Change-Id: Ic9b7e065b7303b3707c28c9b7c496cc1c1e91acd
2017-02-14 12:55:03 -08:00
Tim Newsome ae4fda2719 Make it all the way through examine().
This includes reading GPRs (although I haven't confirmed the values) and
doing some CSR reading/writing to disable triggers that may be left over
from a previous setting.

Change-Id: I2c627bd002d601e302a40f838087541897c025fd
2017-02-14 11:43:58 -08:00
Tim Newsome 00925574d5 More dbus->dmi.
Change-Id: Ia691f1e7ce909da4d9c16e6d691c4f2cf768a7fb
2017-02-14 09:38:09 -08:00
Tim Newsome 24033b53d8 Read misa during examine(), using program buffer.
Change-Id: Icad5324d216b61207cb5f6024b2deab065658640
2017-02-13 21:29:02 -08:00
Tim Newsome 0fa8162a8c dbus -> dmi
Change-Id: I4c3343f8f5ffd45e3d76a2218aaa5dee8e546839
2017-02-13 11:13:14 -08:00
Tim Newsome e2a5e02d1c Discover XLEN using abstract reg reads.
Change-Id: Ib7480b8e4925cf08e5b59d263bcdcc672a89dc4b
2017-02-13 09:54:05 -08:00
Karl Palsson 091c378728 flash/nor: avrf: support atmega128rfa1
Tested with a Dresden Elektronik deRFmega128 module.

Change-Id: I91da3b11b60e78755360b08453ed368d6d396651
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/2790
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-13 17:42:36 +00:00
Tim Newsome e6221e75c9 Attempt to discover XLEN with abstract reg reads
Change-Id: I7ce9c8c0c34bd875dba11596e6f6268320b2fb3a
2017-02-10 19:08:44 -08:00
Megan Wachs 3a1d6f1702 riscv: Add register name to message when they do not exist. 2017-02-10 14:19:23 -08:00
Tim Newsome 5e3d9803ab Halt target in riscv_examine().
Change-Id: I11ab915901f2e75f9b728d6cf72c6498e3950ded
2017-02-10 11:31:14 -08:00
Matthias Welwarsky 7c2dc138b3 aarch64: don't try resuming if target is not halted
At framework level, the resume hook is not protected. Make sure to
not attempt a resume if the target is not halted.

Change-Id: I4dd1975a95d6c513bd4f4e999e496bc11182a97a
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky beece50670 aarch64: don't segfault on reset when target is not examined
Basically port a fix that was already done for the cortex_a target.

Change-Id: I4cf4519159bda03ed611bc0b2e340a5dad2d85fe
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky 9d2e8aabb8 aarch64: use cached value of dscr register where needed
Instead of supplying a local, preinitialized "dscr" variable, use the
cached value from arm_dpm, which is kept up-to-date anyway.

Change-Id: I06d548d4dc6db68b9d984c83ed026fa9069d7875
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky 9166320663 aarch64: remove arm command chain from aarch64 target commands
arm commands are mostly unusable anyway, remove them. to be replaced
by aarch64 specific commands later

Change-Id: Ie994771bc0e86cff1c26f68f1f51ce8ec352a509
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky 8f59ee3871 aarch64: remove "mrs <Xt>, currentel" opcode
"currentel" special register is not accessible in debug state.

Change-Id: I9022b01b423cd9ae8227ed018d6166078ba44832
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky 2407721e14 aarch64: remove unused struct components
remove unused register index array from armv8_mode_data[]

Change-Id: I686c20eeb3da413f5e9ef6058e31ce939741afb4
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky 7d537dc8e9 aarch64: improve debug output
Make debug and error messages more informative, fix spelling and
formatting errors

Change-Id: I7245f42c5153bcc95676270814d30e91c113aaed
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky 822ebda674 aarch64: enlarge value buffer of arm_reg to store 64 bit
struct arm_reg::value[] must be 8 byte to hold a 64bit register value.

Change-Id: If253e90731d0ee855eafd9d7b63b91f84630cc7c
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky f7dbcc3fab aarch64: consolidate sticky error handling
Move clearing of DSCR "Sticky Error" condition to the
exception handling function. Clear once on entering debug state.

Change-Id: Iec1d09d6f2d9cdd7e92953da5ea19f3e399ca12c
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky 9f4b5b509f aarch64: discard async aborts on entering debug state
recommended for Corte-A8 cores, not sure if necessary
for ARMv8 based cores as well.

Change-Id: Ibcb36170c5fac6a6b132de17f734c70a56919f9b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky 0a53bae0ea aarch64: cleanup context restore
Remove register cache invalidation and target state changes that are
handled appropriately in other functions.

Change-Id: Ic903f41ddc267f4b8765ea022bd4d6da1017e21f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky ccb1199d49 aarch64: enable aarch32 debugging with arm gdb
When a PE is in Aarch32 state and gdb asks for a target description,
provide a register view compatible with the "org.gnu.gdb.arm.core"
feature. Only current-mode registers are exported, banked registers are
not visible.

Change-Id: I99a85d94831cf597fe8cff6a0a1818ce0a33613b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky ba82230856 aarch64: allow reading TTBR register when halted in EL0
There's no access to TTBR in EL0. Circumvent by moving the PE to EL1
before reading, and switch back to original mode afterwards.

Change-Id: I22891b958d3d7e6fad1cb27183c192d975d63d89
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky 05bf20d05a aarch64: make sure to enable HDE for all SMP PEs to be halted
When halting a group of PEs through CTI, HDE must be set in EDSCR for
all of them.

Change-Id: Iaa4bc0b0fe31e46a463c709d8274023225affd85
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky c30f8d6a07 aarch64: handle exceptions taken in debug state
When an armv8-a PE causes an exception while halted, e.g. by performing
a prohibited memory or register access, its state is affected in the
same way as if it was running. That means, a number of registers is
overwritten (notably DLR and DSPSR, but also others) and also
potentially the exception level and therefore also the PE state can
change. This state must be restored before resuming normal operation.

This is done by marking the relevant cached registers "dirty" so that
they are written back before resume.

Change-Id: I9b6967a62d7cb23a477a9f7839f8d2b7087eed09
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:35 +01:00
Matthias Welwarsky 62c2eb4b28 aarch64: cache identification for aarch32 state
Use proper T32 opcodes for cache identification when the PE is in
Aarch32 state

Change-Id: I9cd9169409889273a3fd61167f388e68d8dde86d
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:34 +01:00
Matthias Welwarsky 946958cb72 aarch64: fix mode switching
DCPS only allows to enter higher ELs, for lower ELs you need to
use DRPS. Also, of course the encoding differs between A64 and T32.
Both DCPS and DRPS also clobber DLR and DSPSR, which then need to be
restored on resume.

Change-Id: Ifa3dcfa94212702e57170bd59fd0bb25495fb6fd
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10 14:18:34 +01:00