51ab5a0c8b
Return 5 (SIGBREAK) not 2 (SIGINT) after a step
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GDB seems to just go off the rails if I return a SIGINT.
2017-05-25 18:31:58 -07:00
f0969e7c71
Pass EVENT_RESUMED in the RTOS
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I missed this event. It appears to do nothing.
2017-05-25 13:14:31 -07:00
ab77c5d792
Invalidate the register cache when rtos_hartid==-1
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This means I don't know what hart to look at, so I might as well
invalidate the register cache. Without this, you might get stale
registers the first time you ask for them.
2017-05-25 13:14:31 -07:00
faa6123e36
Invalidate the register cache on step, resume, reset
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I thought OpenOCD did this, but it looks like that doesn't happen when
runningi in RTOS mode. With this I can get to the end of most of the
RTOS tests, but they SIGINT instead of exiting.
2017-05-25 13:14:31 -07:00
a1e07e58f4
Merge pull request #52 from riscv/v11_read_without_int
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riscv-v11: Don't perform unexpected operation in cache_write
2017-05-25 10:51:27 -07:00
e12f5575ef
riscv-v11: Don't perform unexpected operation in cache_write
2017-05-22 22:02:01 -07:00
c431c0eb25
Check for abstractcs.busy, not just CMDERR_BUSY
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This fixes a race condition when reading/writing memory.
2017-05-15 17:40:28 -07:00
a8cf04b839
Go back to 32-word read/write buffers
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The larger buffers are really slow on Spike.
2017-05-15 16:57:25 -07:00
e31761df64
Don't re-read registers after they're written
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This was just a sanity check.
2017-05-15 16:57:08 -07:00
9d308db2bc
Print out the actual CSR that's read
2017-05-15 16:56:50 -07:00
8252b9d36c
Build fixes
2017-05-15 13:39:58 -07:00
af6e04d5c0
riscv: Remove some compile warnings
2017-05-15 13:36:05 -07:00
bcf2a16b0d
Shim back in some old interfaces for now
2017-05-11 10:41:13 -07:00
563f6acc3c
Allow all harts to be reset
2017-05-09 13:33:20 -07:00
fa8d7adf33
Avoid accessing null target->reg_cache
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GDB might request registers even if target was not successfully initialized.
2017-05-05 11:05:28 -07:00
325f17f6ec
Merge pull request #43 from riscv/read-from-0
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Read from 0
2017-05-05 09:30:24 -07:00
95a2eb157a
riscv-013: more consistent parens
2017-05-01 09:42:11 -07:00
458bb20699
riscv-013: Correct sign extension of address on read_memory for lower bits as well
2017-05-01 09:39:59 -07:00
8462750357
riscv-013: Correct sign extension of address on read_memory
2017-05-01 09:37:48 -07:00
ad1cf13ef4
Correct debugging print in read_memory
2017-05-01 08:35:10 -07:00
16de5044d4
Fix an assertion when reading from 0
2017-05-01 08:33:01 -07:00
ba3a56937b
Correct previous hart caching logic
2017-05-01 08:32:43 -07:00
1ec607c726
Clean up unused read_memory code
2017-04-27 12:56:01 -07:00
4116b97d6e
Correct an off-by-one in argument parsing
2017-04-26 15:17:11 -07:00
17d04aded3
Keep calling the old poll on v0.11 targets
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This is another thing that should be fixed correctly. Essentially this
just uses the old codepath, which works for v0.11.
2017-04-26 15:16:39 -07:00
9d4df3420c
Initialize all registers in examine
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I'm not sure why this is necessary, but for some reason GDB is asking
for registers before OpenOCD thinks there's been a halt. This is really
just a workaround, but I need to refactor the v0.11 stuff anyway so I
don't want to figure it out.
2017-04-26 15:09:24 -07:00
da66be0161
riscv: Fix some blocking compile warnings
2017-04-26 10:23:53 -07:00
1ab5d7b497
fespi: Allow the ctrl_base address specified as a parameter
2017-04-26 09:10:49 -07:00
8dea2908b7
Add 64-bit and multihart support
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This is a major rewrite of the RISC-V v0.13 OpenOCD port. This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports. This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around. The changes are:
* You can pass "-rtos riscv" to the target in OpenOCD's configuration
file, which enables multi-hart mode. This uses OpenOCD's RTOS
support to control all the harts from the debug module using commands
like "info threads" in GDB. This support is still expermental.
* There is support for RV64I, but due to OpenOCD limitations we only
support 32-bit physical addresses. I hope to remedy this by rebasing
onto the latest OpenOCD release, which I've heard should fix this.
* This matches the latest draft version of the RISC-V debug spec, as of
April 26th. This version fixes a number of spec bugs and should be
close to the final debug spec.
2017-04-26 09:10:49 -07:00
3dc066382b
Properly consider 'reset halt' and do halt or resume as needed
2017-04-10 12:03:15 -07:00
75e7c79b2a
fespi: Reset may have occurred. Need to set TXWM again. There are probably more places that need this added.
2017-04-10 12:03:15 -07:00
b04c6cb3ed
riscv: Implement the assert/deassert reset functions for v13
2017-04-10 12:03:15 -07:00
7203102c25
Merge pull request #28 from sifive/readmem_autoexec
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Readmem autoexec
2017-04-04 22:27:52 -07:00
14e26040b8
riscv: move value read to after autoexec is cleared.
2017-04-04 16:33:17 -07:00
9c1f6ea28b
riscv: Correct the autoexec in read_mem
2017-04-04 16:22:55 -07:00
69a8273da5
Merge pull request #23 from sifive/w1-to-clear-cmderr
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riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.
2017-03-30 15:10:56 -07:00
eb90a5e05e
riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.
2017-03-30 14:27:28 -07:00
7df6804934
Revert "(WIP) Force algorithms to 64 bit"
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This reverts commit 466b7b4881
2017-03-23 19:46:54 -07:00
466b7b4881
(WIP) Force algorithms to 64 bit
2017-03-23 19:21:02 -07:00
ae51b92480
some device
2017-03-23 14:51:30 -07:00
03fa9d22c4
Don't set abstractauto at the start
2017-03-23 14:50:40 -07:00
84fa7aa916
Merge pull request #21 from sifive/read_memory_retry
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Read memory retry
2017-03-22 18:00:44 -07:00
a7499161e0
Merge remote-tracking branch 'origin/riscv' into read_memory_retry
2017-03-22 17:53:23 -07:00
c61b3efe9a
riscv: Retry failed memory reads
2017-03-22 17:51:46 -07:00
5f9cc2ce5f
Turn off autoexec after read_memory()
2017-03-22 14:28:39 -07:00
98420e377a
riscv: add missing variable declaration.
2017-03-21 23:47:21 -07:00
09da0c812f
Clear autoexec correctly
2017-03-21 17:20:11 -07:00
6033850415
Wrong autoexec
2017-03-21 17:20:11 -07:00
0c790d385d
Builds
2017-03-21 17:20:11 -07:00
c09ccbcc7c
Merge pull request #20 from sifive/delay_after_autoexec
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riscv-v13: wait for idle in read_memory
2017-03-21 13:18:26 -07:00
Palmer Dabbelt
Megan Wachs