During ROM table parsing, each ROM table entry points to a
CoreSight component that can, in turn, be another ROM table.
Split the specific code for ROM table handling from the generic
CoreSight code.
Log an error if a ROM table entry cannot be read.
Change-Id: I5ad106a99b9c21ddb48b5b162ae87101e4f49878
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6816
Tested-by: jenkins
Rework dap_read_part_id() while preparing for reorganizing the
'ROM Table Parsing' (RTP):
- rename it with 'rtp' prefix;
- extends it to read other CoreSight registers, thus improving the
overall speed by queuing more reads;
- reduce the list of arguments by using a struct;
- reorder the reads by increasing offset, potentially gaining
speed using MEM_AP_REG_BDx and/or auto-increment;
- log a debug message in case of read error.
Change-Id: I6544ac7740b808a6c0fbacf97ac00b97f5bd3832
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6815
Tested-by: jenkins
ADI v5.1 and v6.0 permit the definition of CoreSight components (class 9
ROM entries).
dap_rom_display() is refactored a bit such that we always end up with
attempting to parse the ROM contents using the appropriate upper limit
for class 1 and 9 ROM types.
Change-Id: I4ba497b3807f1f11f06186eb6e61959ea3540c59
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6359
Tested-by: jenkins
Use the list of values from ARM IHI0029E to decode and print the
Device Architecture register.
Add attribute 'unused' to the function, not used yet.
Change-Id: I7b1dd204bd1db671578c588372b667e23611876c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6463
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
In case of AP not responding, e.g. not clocked, the first WAIT
reply is logged as:
DAP transaction stalled (WAIT) - slowing down
then OpenOCD retries the transaction few times, until it timeouts.
At each retry it prints the message:
DAP transaction stalled during replay (WAIT) - resending
Depending on JTAG speed and transport latency, the amount of log
messages can be quite annoying and not relevant.
The last printed line is at timeout:
Timeout during WAIT recovery
Reduce the verbosity.
Change-Id: I5a7a337527c98b2450de59066b13713511c2894f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6814
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Right now it has a single use but it will soon be used more.
Change-Id: I9a819c65df467fc859e4b5251035a17ed33daa35
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6813
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
In jimtcl 0.80 the prototype of Jim_DictPairs() has changed.
The only code in OpenOCD that uses Jim_DictPairs() has been merged
recently and it only uses the current jimtcl syntax.
To allow compiling OpenOCD master branch with older versions of
jimtcl, detect the version of jimtcl and use the appropriate
syntax.
Change-Id: I6fc78303b6a4db064a97f326c46119f4568e88f3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: dullfire@yahoo.com
Reviewed-on: https://review.openocd.org/c/openocd/+/6948
Tested-by: jenkins
The deprecation was already in the documentation since v0.11.0
through commit 85ba2dc4c6 ("rtos/hwthread: add hardware-thread
pseudo rtos") but OpenOCD was not informing the user printing a
runtime message.
Remove the deprecated method from the documentation and print a
deprecated message at runtime.
There is no reliable way to print the same message in GDB console,
so we have to rely on user noticing it in the OpenOCD log.
Target is to remove the functionality after v0.12.0.
Change-Id: Idd2d9e3b6eccc92dcf0432c3c7de2f8a0fcabe9f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6862
Tested-by: jenkins
on macos (homebrew base) `pkg-config --cflags capstone` output with
`-I/opt/homebrew/Cellar/capstone/4.0.2/include/capstone`
gcc not find headers on parent "include" path,
causes build error `fatal error: 'capstone/capstone.h' file not found`
it's ok to change to <capstone.h> for all platforms.
Signed-off-by: fatalc <cnfatal@gmail.com>
Change-Id: Ia2e2058024d4fc1a57a8b4ea847c664d74f67efb
Reviewed-on: https://review.openocd.org/c/openocd/+/6946
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Handle JIM_CONTINUE return value of adiv5_jim_mem_ap_spot_configure(),
otherwise OpenOCD silently quits when an unknown option is provided.
Change-Id: I9b1351c0911e74999d8dd1260ede9760088510d7
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6944
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixed the reading of p_flags in ELF64 segment headers - that field
is 64 bits wide.
Change-Id: I053ca57d36efb54b7c638484acd6c7a2fbcbd05a
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6927
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Including config.h as first is required for every C file.
Add it to the C files that still miss it.
Change-Id: I1a210e7d3a854958a85a290b086ad8a9f5176425
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6856
Tested-by: jenkins
While the documentation reports that SWO pin frequency can be
omitted to let the adapter autodetect the value, the code wrongly
drops an error when pin frequency is not specified.
Don't require the pin frequency to be set at "enable", but verify
that the adapter has properly changes it to a valid value.
Change-Id: I3dfbe3256e8887ef4f03512769b06381cdc9db0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Karl Palsson <karlp@tweak.net.au>
Fixes: 184724d14e ("arm_tpiu_swo: add support for independent TPIU and SWO")
Reviewed-on: https://review.openocd.org/c/openocd/+/6310
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Commit dbbac5f11d ("semihosting: use open mode flags from GDB,
not from sys/stat.h") fixes the conversion of the mode flags from
ARM semihosting encoding for SEMIHOSTING_SYS_OPEN to GDB mapping
for open().
Doing this, it breaks the conversion to local host's OS mapping
for open().
Split the conversion array to one for GDB and one for local host.
The local host conversion array is taken directly from the old
code.
Change-Id: I385321ddd32c3ac5cf6da3f1ce9eff76b05dd527
Fixes: dbbac5f11d ("semihosting: use open mode flags from GDB, not from sys/stat.h")
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6870
Tested-by: jenkins
Some configuration of GCC could default to -fno-inline, causing
the build to fail after commit fb43f1ff4e ("target: Rework 'set'
variable of break-/watchpoints").
Switch the new inline functions to 'static inline', as it's widely
used in the rest of the code.
Change-Id: I8bf31045a137bd34ed825f4b2a9338eb3c70046d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: fb43f1ff4e ("target: Rework 'set' variable of break-/watchpoints")
Reviewed-on: https://review.openocd.org/c/openocd/+/6881
Tested-by: jenkins
The 'set' variable name suggests a boolean data type which determines
whether a breakpoint (or watchpoint) is active. However, it is also
used to store the number of the breakpoint.
This encoding leads to inconsistent value assignments: boolean and
integer values are mixed. Also, associated hardware comparator
numbers, which are usually numbered from 0, cannot be used directly.
An additional offset is required to store the comparator numbers.
In order to make the code more readable and the value assignment more
consistent, change the variable name to 'is_set', its data type to 'bool'
and introduce a dedicated variable for the break-/watchpoint
number.
In order to make the review easier, the data types of various related
variables (e.g. number of breakpoints) are not changed.
While at it, fix a few coding style issues.
Change-Id: I2193f5639247cce6b80580d4c1c6afee916aeb82
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6319
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This command permits the usage of a TCP port to perform debug and stdio
operations:
- debug : READC, WRITEC and WRITE0
- stdio : READ, WRITE
This will permit the separation of semihosting message from OpenOCD log,
and separate semihosting messages per core.
syntax: arm semihosting_redirect (disable | tcp <port> [debug|stdio|all])
this allows to select which operations to be performed via TCP (debug,
stdio or all (default)).
Note: for stdio operations, only I/O from/to ':tt' file descriptors are
redirected.
tested using netcat on ubuntu
Change-Id: I37053463667ba109d52429d4f98bc98d0ede298d
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5562
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
To easily add new methods to a service, pass all the methods
through a struct.
While there, drop the typedef for the methods and add currently
unused new methods to support keep-alive and connections during
keep-alive.
No change in functionality.
Change-Id: I2b5e7140db95021f6e7201e9d631ee340c60b453
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6838
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Replace 'mem2array' and 'array2mem' with a Tcl wrapper that
internally uses 'read_memory' and 'write_memory'.
The target-specific 'mem2array' and 'array2mem' functions
remain for now.
Change-Id: If24c22a76ac72d4c26916a95f7f17902b41b6d9e
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6308
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
These functions are meant as replacement for 'mem2array' and
'array2mem'.
The main benefits of these new functions are:
* They do not use Tcl arrays but lists which makes it easier
to parse (generate) the data. See the Python Tcl RPC code
in contrib as a negative example.
* They do not operate on Tcl variables but instead return (accept)
the Tcl list directly. This makes the C and Tcl code base
smaller and cleaner.
* The code is slightly more performant when reading / writing
large amount of data. Tested with a simple Python Tcl RPC
benchmark.
Change-Id: Ibd6ece3360c0d002abaadc37f078b10a8bb606f8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6307
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The current implementation crashes when executing 'tpiu create'
without an object name due to an invalid memory access. Pass 'argv'
instead 'goi.argv' to fix the problem.
While at it, match the style of the error message to the style used for
other Tcl commands. Especially, make the 'name' parameter mandatory.
Change-Id: Ib2b233f8556934af61608ae93d6405585c2c40b7
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6329
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The getter checks the magic numbers in arch_info to detect eventual
type mismatch.
Change-Id: I61134b05310a97ae9831517d0516c7b4240d35a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6751
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
target_to_armv7m() and target_to_cm() do not match the magic number
so they are not suitable for use outside of target driver code.
Add checked versions of pointer getters. Match the magic number
to ensure the returned value points to struct of the correct type.
Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6750
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The third parameter of container_of() should point to the same member
as target->arch_info points to, struct arm.
It worked just because struct arm is the first member in
struct armv7m_common.
If you move arm member from the first place, OpenOCD fails heavily.
Change-Id: I0c0a5221490945563e17a0a34d99a603f1d6c2ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6749
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This functionality was lost in [1], which was merged as commit
615709d140 ("Upstream a whole host of RISC-V changes.").
Now it works as expected again.
Add convenience macro foreach_smp_target_direction().
Link: [1] https://github.com/riscv/riscv-openocd/pull/567
Change-Id: I1545fa6b45b8a07e27c8ff9dcdcfa2fc4f950cd1
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6785
Tested-by: jenkins
Instead of reinventing a simply linked list, reuse the list helper
for the list of targets in a smp cluster.
Using the existing helper, that implements a double linked list,
makes trivial going through the list in reverse order.
Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6783
Tested-by: jenkins
Enabling a portion (0x100 - 0x107) of the user defined semihosting
operation number range (0x100 - 0x1FF) to be processed with the help of
the existing target event mechanism, to implement a general-purpose Tcl
interface for the target available on the host, via semihosting
interface.
Example usage:
- The user configures a Tcl command as a callback for one of the newly
defined events (semihosting-user-cmd-0x10X) in the configuration
file.
- The target can make a semihosting call with <opnum>, passing optional
parameters for the call.
If there is no callback registered to the user defined operation number,
nothing happens.
Example usage: Configure RTT automatically with the exact, linked
control block location from target.
Signed-off-by: Zoltán Dudás <zedudi@gmail.com>
Change-Id: I10e1784b1fecd4e630d78df81cb44bf1aa2fc247
Reviewed-on: https://review.openocd.org/c/openocd/+/6748
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Values defined in sys/stat.h are not guaranteed to match
the constants defined by the GDB remote protocol, which are defined in
https://sourceware.org/gdb/onlinedocs/gdb/Open-Flags.html#Open-Flags.
On my local system (Manjaro 21.2.1 x86_64), for example, O_TRUNC is
defined as 0x40, whereas GDB requires it to be 0x400,
causing all "w" file open modes to misbehave.
This patch has been tested with STM32F446.
Change-Id: Ifb2c740fd689e71d6f1a4bde1edaecd76fdca910
Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6804
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
We have the API target_event_name().
Use it to improve code readability.
Change-Id: Ic48d2227bdefe9af05aff99a871a45e0612e5254
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6790
Tested-by: jenkins
If the CTI is not specified OpenOCD fails target's examination
without indicating the reason.
Drop an error message about the missing CTI.
Change-Id: I344537fb21cf38785796ba938e71890e04135509
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6788
Tested-by: jenkins
This replaces a static array with 8 bytes per register. When there are
vector registers larger than 8 bytes, they would end up clobbering each
other's values. I can't believe I didn't catch this earlier.
See https://github.com/riscv/riscv-openocd/pull/658
Change-Id: I9df4eaf05617a2c8df3140fff9fe53f61ab2b261
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6775
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
We have the macro
#define COMMAND_HANDLER(name) \
static __COMMAND_HANDLER(name)
Use it!
Change-Id: I0e5385cb54197c743348f0d2ce215c93b8e396a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6786
Tested-by: jenkins
Unlike cortex_m_load_core_reg_u32() storing core register uses
the same code pattern around DHCSR read as offered by the convenience
helper cortex_m_read_dhcsr_atomic_sticky().
Use the helper.
Change-Id: Ia947204944a8b549f3c2be7fb2f717aad18970c4
SeeAlso: 65d7629183 (cortex_m: poll S_REGRDY on register r/w)
SeeAlso: 0dcf95c717 (target/cortex_m: cumulate DHCSR sticky bits)
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6767
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Change [1] introduced a regression that results in comparison
in arm_jtag_set_instr() to be always true if the length of the
IR register is not 8 bit. The value on the left side
of the != operator contains only tap->ir_length number of
bits while value on the right is full 8-bit instruction code.
This forces OpenOCD to update the JTAG IR register on each
transaction even if the instruction in the JTAG IR register
is correct. This causes noticeable performance degradation,
especially with slow JTAG adapters.
[1] https://review.openocd.org/c/openocd/+/6285
time ./src/openocd -s tcl/ -f interface/cmsis-dap.cfg \
-c "transport select jtag" -f target/psoc6.cfg \
-c "init; load_image data.bin 0x08000000; exit"
Without this change:
real 0m4,863s
user 0m0,074s
sys 0m0,128s
With this change:
real 0m3,083s
user 0m0,038s
sys 0m0,098s
Signed-off-by: Bohdan Tymkiv <bohdan200@gmail.com>
Change-Id: Iaded83a04ecc7e65f18256afae582267ccc1fc59
Reviewed-on: https://review.openocd.org/c/openocd/+/6762
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
ARM IHI 0031A does not support SWJ-DP, so no switch between JTAG
and SWD is considered.
ARM IHI 0031B is not publicly available and it's reported as
"Confidential Beta" in the history list in following doc versions.
From ARM IHI 0031C the direct switch between JTAG and SWD is
already deprecated in favor of passing through dormant mode. With
no access to IHI 0031B we haven't info if any device strictly
requires the direct switch.
OpenOCD implements only the deprecated direct switch, so changing
it could cause regression on devices that do not implement dormant
mode.
Plus, not all the adapters support dormant mode.
Nevertheless there are already target devices that only allow
entering in SWD by passing through dormant.
Let the code try both method, alternating one tentative with the
deprecated legacy direct switch, then another tentative passing
through dormant, and repeat till timeout.
This would work on any device that don't support dormant, on new
devices that require switch through dormant and will work with
adapters that don't support dormant.
Change-Id: Ib8619635277d497872079a33fa4e38be9beb84a0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6695
Tested-by: jenkins
The function debugport_init() has never existed in OpenOCD code,
but few comments erroneously references it in place of the
existing function ahbap_debugport_init().
Commit 00dbc185ee ("arm_adi_v5: Split ahbap_debugport_init")
splits the function ahbap_debugport_init() in dap_dp_init() and
mem_ap_init(), but did not removed all the incorrect comments
about debugport_init(). Few of such comments has been removed in
later patches.
Remove the last comment that references debugport_init().
Change-Id: Ibd1f125475386e5653340fedf706903a0ee15897
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6694
Tested-by: jenkins
Standard C library free() allows NULL pointer as a parameter.
Change target_free_working_area() to conform this convention.
Remove NULL pointer tests before target_free_working_area() calls.
While on it add missing setting pointer to NULL after target_free_working_area().
Change-Id: I7c692ab04a9933398ba5bc614723ad0bdecb87b3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6712
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
hla_target uses the same struct cortex_m_common as the standard cortex_m
target. Unlike the cortex_m target hla missed setting of common_magic.
Set commont_magic to help pointer verification.
Add convenience tests is_cortex_m_or_hla() and
is_cortex_m_with_dap_access()
Use proper test in cortex_m_verify_pointer() - this code relied on
unset common_magic on hla target before the change.
Change-Id: I4dae79f056c3d73adf524e26aa8ef2d3a57b471e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6741
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Just to avoid name clash when comparing documentation with
registered commands through scripts.
Change-Id: I8832545d8d9236ea5dabe6e73732f51e5246caff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6717
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Do not split in multiple lines the calls to register_commands*().
No change in code behaviour, just make it easy to grep in the code
and identify the commands that can be registered.
This would help detecting undocumented commands.
Change-Id: Id654e107cdabf7ee31fc3d227c1d2a59acc5669e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6716
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Raise error if
* more than one plain SWD DAPs are defined
* plain and multidrop DAPs are mixed
* two multidrop DAPs have the same TARGETSEL value
Inspired by Graham Sanderson's http://review.openocd.org/4935
Change-Id: I7279744464f5cc6477e50695c596be9c5e5507bf
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6142
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Based on Graham Sanderson's http://review.openocd.org/4935
Unlike Graham Sanderson's version this patch does not add
any multidrop specific queuing.
Multidrop SWD is handled mostly by the same code as single SWD,
just a selection sequence is prepended to a SWD operation
as needed.
This is a minimal working implementation without checking for
configuration errors (mixing multidrop and non multidrop DPs,
multiple use of the same selection id etc...).
Multidrop switching likely demands changes in the adapter code.
Change-Id: I99a5742c209b49c0483e800f6105cb5e59a897d9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6141
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
dap_configure() contained first time init related tasks, as the call to
dap_init_instance() and the check for configured tap.
Move all first time init related stuff to dap_create() to make dap_configure()
usable in eventual stand-alone 'dap configure' command.
Change-Id: Ia86eadb4e960ce54e8581630d01af75720d2318d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6702
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This is a preparatory change for swd multidrop, mostly refactoring.
Split swd_queue_dp_read/write() to inner and outer parts.
Use the inner parts in swd_queue_dp_bankselect(), swd_connect()
they do not need to check reconnect.
Use the outer parts exclusively in swd_dap_ops.
Rearrange the code to reduce forward declarations.
Change-Id: I47b7f0cb037e0032a267463f06ba02123ba96fe7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6139
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
I missed this when I first add mcontrol6 support.
https://github.com/riscv/riscv-openocd/pull/648
Change-Id: I1a2706c7ea3a6757ed5083091cd2c764a8b0267c
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6684
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The main intention is to get access to some of the CSRs
that were so far unknown to OpenOCD (tinfo, mcountinhibit, ...).
https://github.com/riscv/riscv-openocd/pull/659
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I824fdb558d5c1f73432b0f56f3b0b4d865eceeba
Reviewed-on: https://review.openocd.org/c/openocd/+/6682
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add the value DORMANT_TO_JTAG in the enum listing the SWJ-DP
switching sequences.
The corresponding bit-sequence is already available.
Change-Id: I6f1ffd29a8f5729ec70ce0303248bc251409d37d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6689
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
If the target is in a state where S_REGRDY polling is necessary (slow
clock, low power state...?), OpenOCD will continue to use the slow
path even if the condition is temporary and the target at a later
point would be capable of fast reads again.
Revert to fast reads if a full register dump can be made without need
for polling any of the registers; presumably it will succeed the next
time too.
Change-Id: I557f0d90b7ce6f9d81aa409b6400fc9c83d16008
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6678
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Without the change cortex_m_debug_entry() reads all registers
calling cortex_m_load_core_reg_u32() for each register with
a poor usage of JTAG/SWD queue.
It is time consuming, especially on an USB FS based adapter.
Moreover if target_request debugmsgs are enabled, DCB_DCRDR
is saved and restored on each register read.
This change introduces cortex_m_fast_read_all_regs()
which queues all register reads and a single dap_run() transaction
does all work.
cortex_m_fast_read_all_regs() reads all registers unconditionally
regardless register cache is valid or not. This is a difference
from the original cortex_m_debug_entry() code.
cortex_m_debug_entry times from -d3 log, Cortex-M4F and CMSIS-DAP
(Kinetis K28F-FRDM kit)
target_request | time [ms]
debugmsgs | without the change | with the change
---------------+--------------------+-----------------
disable | 186 | 27
enable | 232 | 29
Added checking of DHCSR.S_REGRDY flag. If "not ready" is seen,
cortex_m->slow_register_read is set and fallback to the old
register read method cortex_m_slow_read_all_regs() is used
instead of cortex_m_fast_read_all_regs().
Change-Id: I0665d94b97ede217394640871dc451ec93410254
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/5321
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Accordingly to arm documentation [1], chapter C1.6.4, the
operation to read/write from/to core registers can require time,
and the specific flag DHCSR.S_REGRDY has to be polled to verify
that the operation has been completed.
The lack of check on S_REGRDY causes OpenOCD to fail handling
correctly the core registers on a Cortex-M4 emulated in a slow
FPGA, and it could also fail on devices clocked at very low speed
while using a fast adapter.
Poll S_REGRDY as specified in [1] while either reading or writing
the core registers.
A timeout of 0.5s is added. This could still be too small in some
extremely slow cases, but at least now we log the timeout event,
which can help tracking down such odd issue.
During register read include in the polling loop the read of DCRSR
and to flush the JTAG queue only once.
During register write, relax the write in DCRSR by removing the
atomicity that is now useless since followed by the atomic read to
S_REGRDY.
During register read include the read of DCRSR inside the polling
loop to relax the read of S_REGRDY since followed by the atomic
read to DCRSR.
This change has the drawback of adding other transfers to the
adapter while reading/writing the registers, so it is expected to
introduce some speed degradation during step-by-step.
[1] DDI0403E - "ARMv7-M Architecture Reference Manual"
Change-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/5319
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
DCB DHCSR register contains S_RETIRE_ST and S_RESET_ST bits cleared
on a read.
The change introduces a helper function cortex_m_cumulate_dhcsr_sticky().
Call this function each time DHCSR is read to preserve S_RESET_ST state
in the case of a reset event was detected.
Introduce cortex_m_read_dhcsr_atomic_sticky() convenience helper to
read DHCSR, store it to cortex_m->dcb_dhcsr and cumulate sticky bits.
The cumulated state of S_RESET_ST is read and cleared in cortex_m_poll()
Change-Id: Ib679599f850fd219fb9418c6ff32eed7cf5740da
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6180
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
cortex_m->dcb_dhcsr caches status of DHCSR register.
Use it instead of local variable in cortex_m_soft_reset_halt()
like in other code.
Extracted from [1].
[1] Antonio Borneo: 6207: cortex_m: rework handling of dcb_dhcsr
Link: https://review.openocd.org/c/openocd/+/6207
Change-Id: I9a0aeba0b6b0b4969f05f4a32fc2fc8d244f56ca
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6677
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
cortex_m_single_step_core() used mem_ap_write_atomic_u32() to manipulate
dhcsr bits unlike the rest of code, where a specialized function
cortex_m_write_debug_halt_mask() takes place.
Unify setting of dhcsr bits and use cortex_m_write_debug_halt_mask() here as well.
Extracted from [1].
[1] Antonio Borneo: 6207: cortex_m: rework handling of dcb_dhcsr
Link: https://review.openocd.org/c/openocd/+/6207
Change-Id: I9ef05ce88a9dce42e1d3d5404a4fe87ec86b5fe8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6676
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
After moved the code, align the include files.
Change-Id: I514a3020648816810d69f76c2ec4f6e52a1c57ab
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6643
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Doxygen cannot resolve the path of the files in folder contrib.
Use a path relative to current folder, as done in other files.
Change-Id: If39b416ed422b4854dd108777fa32dd4c809450a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6635
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
There is no reason to add the 'src' prefix.
Remove it.
Change-Id: Id7d7ee8b3807fb90381cc1d6d545321020bc06c1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6634
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Made no attempt to separate this out into reviewable chunks, since this
is all RISC-V-specific code developed at
https://github.com/riscv/riscv-openocd
Memory sample and repeat read functionality was left out of this change
since it requires some target-independent changes that I'll upstream
some other time.
Change-Id: I92917c86d549c232cbf36ffbfefc93331c05accd
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6529
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Clang scan-build complains for three dead assignments:
Although the value stored to 'data' is used in the
enclosing expression, the value is never actually read
from 'data'
Value stored to 'address' is never read
Remove the useless assignment and the variable 'data'.
Change-Id: Ie8dcb74b1c1aa5eea1acd06b3c45c5b44954c9e7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6592
Tested-by: jenkins
Clang scan-build complains for a dead assignment:
Value stored to 'tapstatus' is never read
Remove the assignment and add a comment to point for a potential
removal of the line.
Change-Id: Iad2fdc7e6faf650e24cc086ee74c745acb0d1c73
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6591
Tested-by: jenkins
Clang scan-build complains for five dead assignments:
Value stored to 'retval' is never read
Check the returned value and propagate the error.
Change-Id: I01172887a056d6f39ddcf2807848423970db1e89
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6590
Tested-by: jenkins
Clang scan-build complains for two dead assignments:
Value stored to 'r' is never read
Use the variable in the following line, instead of re-computing
the pointer.
Change-Id: I5d4069872be9da85fb28bbe0a82020b90f1efe46
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6589
Tested-by: jenkins
Clang scan-build complains for two dead assignments:
Value stored to 'retval' is never read
Since the timer callback should not return error, print an error
message if the data cannot be send out. Add a FIXME comment
because in current code there is no string/name to report which
connection has failed.
In command tpiu enable check the returned value and propagate the
error.
Change-Id: I9a89e4c4f7b677e8222b2df09a31b2478ac9ca4f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6588
Tested-by: jenkins
The header files under src/helper/ can currently be included with
either
#include <bits.h>
or
#include <helper/bits.h>
This is because we specify both "src/" and "src/helper/" directories
as include directories. Some files name under "src/helper/", such as
types.h, log.h, and util.h are too generic and could be ambiguous
depending on the search path.
This commit remove "src/helper/" from our include dir and make C files
include explicitly.
Change-Id: I38fc9b96ba01a513d4a72757d40007e21b502f25
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6507
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For example: before this change in cortex_m_examine, if we fail reading CPUID
we return a failure code but target was set to examined which is not consistent.
Change-Id: I9f0ebe8f811849e54d1b350b0db506cb3fdd58f4
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6548
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Giving the example of STM32WL55x the examine log is the following:
Info : stm32wlx.cpu0: hardware has 6 breakpoints, 4 watchpoints
Info : stm32wlx.cpu1: hardware has 4 breakpoints, 2 watchpoints
After this change the examine log becomes:
Info : stm32wlx.cpu0: Cortex-M4 r0p1 processor detected
Info : stm32wlx.cpu0: target has 6 breakpoints, 4 watchpoints
Info : stm32wlx.cpu1: Cortex-M0+ r0p1 processor detected
Info : stm32wlx.cpu1: target has 4 breakpoints, 2 watchpoints
Change-Id: I1873a75eb76f0819342c441129427b38e984f0df
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6553
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The jimtcl API Jim_GetCommand() sets an error message when the
command is not found and flag JIM_ERRMSG is set.
OpenOCD is checking if the command has already been registered,
thus 'command not found' is the desired case.
Pass flag JIM_NONE to prevent jimtcl from setting the error
message.
Change-Id: I3329c2f8722eda0cc9a5f9cbd888a37915b46107
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6562
Tested-by: jenkins
Commit dc7b32ea4a ("armv7m_trace: get rid of the old tpiu code")
is not handling correctly the old 'tpiu' command if it is run
during the config phase (before command 'init').
Move the call to the old event handler 'trace-config' in function
jim_arm_tpiu_swo_enable(), so it is correctly executed after
'init'.
Add the call to the old event handler 'trace-config' also during
jim_arm_tpiu_swo_disable(), to match the old behaviour.
Add more information while alerting that the event 'trace-config'
is deprecated.
Change-Id: If831d9159b4634c74e19c04099d041a6e2be3f2a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: dc7b32ea4a ("armv7m_trace: get rid of the old tpiu code")
Reviewed-on: https://review.openocd.org/c/openocd/+/6561
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
The initial version of the table dap_part_nums contains only the
part number of the device and not the manufacturer ID.
This causes collisions between devices with same part number but
from different manufacturer.
The table has been extended to include the manufacturer JEDEC code
in commit 2f131d3c30 ("ARM ADIv5: CoreSight ROM decode part
number and designer id").
For two old/legacy table's entries reported without manufacturer
code it was defined a special ANY_ID manufacturer, meaning skip
the check for manufacturer!
The two legacy entries report the comment "from OMAP3 memmap", and
thanks to the associated string has been possible through Google
to identify a Master Report [1] about using OpenOCD with the OMAP3
in a BeagleBoard. The ROM table is printed with OpenOCD command
"dap info 1" at page 8 and reports the Peripheral ID required to
extract the manufacturer ID that, out of any surprise, belong to
Texas Instruments.
Set the two missing manufacturer ID to Texas Instruments JEDEC
code.
Remove the now redundant definition and use of ANY_ID.
While revisiting this old code, remove also the useless comment
"0x113: what?". It was introduced in commit ddade10d4a ("ARM
ADIv5: "dap info" gets more readable") and from the same dump in
[1] it's clearly another element in OMAP3. It is listed as entry
0x8 in the ROM table and there is no further info available.
OpenOCD will anyway list it as:
Designer is 0x017, Texas Instruments
Part is 0x113, Unrecognized
Another link https://elinux.org/BeagleBoardOpenOCD reports the
text "Part number 0x113: This is ????", which sounds familiar!
No public document from Texas Instruments reports what is this
device at address 0x54012000.
[1] Warren Clay Grant - University of Texas at Austin
"Implementation of an Open Source JTAG Debugging Development
Chain for the BeagleBoard ARM® Cortex A-8" - May 2012
Link: https://repositories.lib.utexas.edu/bitstream/handle/2152/ETD-UT-2012-05-5478/GRANT-MASTERS-REPORT.pdf
Change-Id: I7e007addbb5c6e90303e4e8c110c7d27810fbe9c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6454
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Extract new part numbers from Arm Cortex-R52 Processor Technical
Reference Manual Revision r1p3 and add them to the array
dap_partnums.
Change-Id: I8020f36de587951af60422ef33d7e438dc7d9d53
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6451
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Extract new part numbers from ARM CoreSight System-on-Chip SoC-600
Technical Reference Manual Revision r4p1 and add them to the array
dap_partnums.
Change-Id: I88d8aa3c084f6e832b75032e75bfb6d377a08360
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6450
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
For readability, move in a separate function the decoding and the
display of devtype register.
The function will be reused with ADIv6.
Split from change https://review.openocd.org/6077/
Change-Id: I7a26a2c9759d5db5f9acfae5c169b90b3deb2f18
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6448
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The complete AP type should include 'class' and 'manufacturer'.
Cleanup the definition of AP type from AP_REG_IDR register.
Include the check of 'class', together with manufacturer and type.
Add the new MEM-AP from ARM IHI0074C.
Change-Id: Ic8db7c040108ba237b54f73b1abe24b8b853699b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6447
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Several magic numbers related to ARM CoreSight specification
IHI0029E are spread around OpenOCD code.
Define through macros the ARM CoreSight magic numbers and collect
them in a single include file.
Use the new macros wherever possible.
Change-Id: I9b0c1c651ce4ffbaf08d31791ef16e95983ee4cb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6446
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
The include file 'armv7m.h' includes 'arm_adi_v5.h' only to get
the definition of 'struct adiv5_ap', but doesn't need the struct
content.
Reducing the cross dependencies speeds-up the compile time during
code development by avoiding re-compiling file.
Relax the dependency by locally declaring 'struct adiv5_ap' in
'armv7m.h' and remove the include of 'arm_adi_v5.h'.
Fix the other files that have now lost the includes file that
'arm_adi_v5.h' depends from.
Change-Id: Ic0d40b17db6045fa43f348bda83eaf211a6b347d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6468
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
NULL is defined as 'void *'.
There is no need to cast NULL while assigning it to a pointer.
Change-Id: Ibaf18e5d47329707ec9c1c184cd4bba2e8e702ff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6540
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
The NULL pointers preceded by cast where not detected by the
scripting tools looking for NULL pointer comparison.
Remove them and, while there, further simplify the code and apply
the other coding style rules.
Change-Id: Ia7406122e07ef56ef311579ab0ee7ddb22c8e4b5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6539
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
This works well with gdb on RISC-V, since hardware breakpoints are
per-core and gdb thinks that targets are really processes on a machine.
Are there targets where this is a bad idea? Should the target definition
specify whether this behavior is desired or not?
Change-Id: Ia32be2707b04347fd8bf2ca6fbb2b0ceaad3704a
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6528
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
As per Arm Debug Interface Architecture Specification (ADIv5.0 to
ADIv5.2), B3.3.1, the JTAG-DP as an IR length of 4 or 8 bits
depending on the ARM implementation. The current code
only support 4-bit and this patch extends the support to 8-bit IR.
Not tested back yet on a 4-bit target.
Change-Id: Ie4f875dc336caf014c6cfced57574b54d0970623
Signed-off-by: Antoine C. <acalando@free.fr>
Reviewed-on: https://review.openocd.org/c/openocd/+/6285
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Current implementation ignores the flag '-ap-num' provided to
command 'target create' and searches for the first AP of APB type.
If specified, use the ap number.
Change-Id: If1ac12345220d14a4a60515efe46dc2a2eac079a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6413
Tested-by: jenkins
JEP106 encodes JEDEC-assigned manufacture code as:
a) a sequence of zero or more escape codes 0x7f;
b) an odd-parity bit of the next 7 bits;
c) 7 bits.
The same code is often represented as a single value composed by
the logical OR between:
- the number of escape codes in a), shifted left by 7 positions;
- the 7 bits in c).
This is the preferred packed representation used by this change.
Currently there are only two uses of JEP106 in openocd to get the
manufacturer name:
- to decode the JTAG IDCODE of each TAP, where the JEP106 code is
already packed as in the preferred representation above in bits
IDCODE[11:1];
- to decode the ARM CoreSight PIDR register, where the JEP106 code
is split in 3 parts:
= PIDR3[3:0], corresponding to bits [10:7] of the packed code;
= PIDR2[2:0], corresponding to bits [6:4] of the packed code;
= PIDR1[7:4], corresponding to bits [3:0] of the packed code.
Wrap the existing JEP106 decode function in a simpler API using
the packed code.
Simplify the callers by skipping the bit unpacking.
Change the manufacturer code in CoreSight table dap_partnums[] to
match the packed representation, by removing the always-one bit 7
erroneously taken from PIDR bit JEDEC and included in the former
table.
Change-Id: I63eb4da9e6801fab25e330f1f6b792d2fd619493
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6418
Tested-by: jenkins
Update the list of ARM coresight classes wrt to latest ARM
documentation.
Use c99 array designator to easily track changes in future.
Add a comment for the entry "OptimoDE DESS". It was added in 2009
by David Brownell, but Google cannot find any reference other than
this line in openocd code its associated commit. It should not be
an issue keeping it as is.
Change-Id: Ia3b646131ee68ca5263095c3a0aeaf75c004b324
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6431
Tested-by: jenkins
The command 'step' accepts an optional parameter 'address' to run
the step-by-step execution from an address different from current
program counter.
When OpenOCD sets the new program counter value in the register
cache, it doesn't flag it as dirty. The following call to function
armv7m_restore_context() does not propagate the new value of the
program counter to the target. This cause the target to continue
from the old program counter value, ignoring the user's request.
It is hard to notice the issue if the target is halted in an idle
loop! In fact the default mode to operate step-by-step is to set a
breakpoint to the following instruction and resume execution. In
the idle loop the CPU will pass through the breakpoint whatever
the resume address is. User will find the target halting at the
instruction following 'address' which is consistent with the
expected behaviour of command 'step address'.
To verify the issue on an STM32F4, use a dummy code in SRAM:
halt
mww 0x20000000 0xbf00bf00
mww 0x20000004 0xbf00bf00
mww 0x20000008 0xe7fcbf00
arm disassemble 0x20000000 6
0x20000000 bf00 nop
0x20000002 bf00 nop
0x20000004 bf00 nop
+--> 0x20000006 bf00 nop
| 0x20000008 bf00 nop
+-<- 0x2000000a e7fc b #0x20000006
resume 0x20000006
halt
step 0x20000000
the target doesn't halt because it is in the loop from 0x20000006
to 0x2000000a. The 'step 0x20000000' did not changed the program
counter so the temporary breakpoint at 0x20000002 is never hit.
Then:
halt
step 0x20000008
target halted ...
... pc: 0x2000000a
gives the feeling that only the instruction at 0x20000008 has been
executed, but actually the whole loop has been executed from the
place 'halt' stopped the execution till the breakpoint at the
instruction following 0x20000008.
Flag the program counter cached value as 'valid' and 'dirty' to
force armv7m_restore_context() to update the target's register.
Change-Id: I49bd8bb95b2f5429ec38ed016f2ad706618ae68a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6434
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Antonio Borneo
Florian Fainelli
Tomas Vanek
fatalc
Marc Schink
Jan Matyas
Tarek BOCHKATI
Tim Newsome
Zoltán Dudás
Pavel Kirienko
Julien Massot
Bohdan Tymkiv
Yasushi SHOJI
Jan Matyas
Andreas Fritiofson
Kevin Burke
root