Commit Graph

338 Commits

Author SHA1 Message Date
Tim Newsome 49dd7ded87 Merge branch 'riscv' into hwthread 2019-01-25 14:17:32 -08:00
Tim Newsome afedcb337a WIP on hardware breakpoints.
This is messy, but contains at least some bugfixes.

39/43 tests pass now.

Change-Id: Ic9e8dad2a0ceb237e28c93906d1cd60876a5766d
2019-01-24 15:27:53 -08:00
Tim Newsome 906635c4bd Move version check until after dmactive=1.
This should allow OpenOCD to work with targets where version is not
readable when dmactive=0, which is allowed by the spec.
2019-01-22 12:48:47 -08:00
Tim Newsome 02ece46105 Clean up register caching a little.
Change-Id: Id039aedac44d9c206ac4bd30eb3ef754e190c3fe
2019-01-10 12:32:03 -08:00
Darius Rad 00b591a09a Add 'riscv set_ir' command to set IR value for JTAG registers.
This allows using different TAP addresses, for example, if using
BSCANE2 primitives on a Xilinx FPGA.
2019-01-09 17:20:39 -05:00
Tim Newsome e6b6aa615b Add comment for reset_delays_wait.
Also refactor so there's just one of them in riscv, instead of one for
0.11 and one for 0.13.

Change-Id: I0dbbf112b4c57f76bed971a22dadf844fa27cd4e
2019-01-08 14:01:25 -08:00
Tim Newsome 6faa9ded26 Clean up debug printf.
I only need to see 64 bits of PC if the high bits are non-zero.

Change-Id: I29397791da1e3f1705e573b2eaafc3eac202e178
2019-01-07 12:16:51 -08:00
Tim Newsome ccc093ab82 Fix typo.
Change-Id: Ibdd26c5c524b10a3518fe708e9b7fc917b0cb1b6
2019-01-02 12:42:31 -08:00
Tim Newsome d6a6699f15 Fix block read corner cases.
Change-Id: I841f264ca881078075beaa58023dd0e0a81f3ff3
2018-12-13 12:05:55 -08:00
Tim Newsome 41e5272adc Add `riscv reset_delays` for testing.
This allows me to test corner cases in block read/write errors.

Change-Id: I3ccfe707851dbc578277ea0d5e278eab81a3c7ef
2018-12-04 12:38:51 -08:00
Tim Newsome d650ef6089 Deal with DMI busy in block reads/writes.
Rename dtmcontrol_idle to dtmcs_idle, because the register is now called
dtmcs.
Simplify read_memory_progbuf_inner(), getting rid of several unnecessary
variables.

Change-Id: Ibac655a45c63cf2210ab282568b54f8097526c10
2018-12-03 16:04:58 -08:00
Tim Newsome 42be17aed6
Add idle count to debug output. (#337)
Few other minor cleanups/debug improvements.

Change-Id: I370a86ddc17a2d888afa178448125661e12caf72
2018-11-29 12:52:06 -08:00
Tim Newsome f042dcb0a3
examine() should leave halted harts halted (#327)
Previously all harts would be resumed at the end of examine().
Fixes #326.

Change-Id: Id82b361e98f151911f8679538ee4b3c754efd6a5
2018-11-12 13:01:55 -08:00
Tim Newsome d18c2f23d3
Doxygen style, too. (#325)
* Doxygen style, too.

Change-Id: I85e60e8577c4177ac7094ae41ee84357b292a89c

* More Doxygen.

Change-Id: Ic7477dce5459146f299e080cac1a3f133af7abdb
2018-11-07 13:53:52 -08:00
Tim Newsome 005cfca219
Install patchutils for the build. (#321)
* Install patchutils for the build.

This contains filterdiff, which we need to check that our changes
conform to OpenOCD style.

Change-Id: Id522f4e62fee3efad4e0e00933abfeada9635624

* Fix paths for filterdiff line.

Change-Id: Ic50e13c7fe64e65b2d2af0260fb19c07a9f10e20

* Conform to OpenOCD style.

Change-Id: I51660d30404c0a625b58c9bed2d948695575e72e
2018-11-05 11:50:09 -08:00
Carsten Gosvig dc4fe85880 Old fixes from June (#311)
* Changed logging level

* Added logging statement

* Removed halt event when attaching to target

* Extended some packet handling

* Extended handling of rtos_hart_id and clearing of register cache

* Extended execute_fence to handle all harts

* Removing logging statement again

* Updated according to review comments

* Forgot to re-add the return statement

* Was removing too much for the if statement to work

* This needs to >= 3 now to handle both a fence and a fence.i
2018-10-30 11:29:00 -07:00
Carsten Gosvig 983a07be64
Merge pull request #308 from riscv/eclipse_memory_read
Fixing Eclipse block memory read
2018-10-19 23:07:22 +02:00
cgsfv 9703c00b25 Moved comment and added initial buffer clearing 2018-10-19 17:47:58 +02:00
Tim Newsome 60c37e1679
dmi_scan() allocate bytes depending on abits value (#307)
* dmi_scan() allocate bytes depending on abits value

Fixes #303.

Change-Id: Iac45959cf342180c60cd0b5462f864ad81beddd2

* Incorporate review feedback.

Change-Id: I1cc7d20fed6f2d891bec0e858fca53ece450720c
2018-10-18 13:26:03 -07:00
cgsfv 0a31d919e3 Corrected wrong C syntax 2018-09-17 13:53:35 -07:00
cgsfv 10a2823191 Read memory words individually if burst read fails 2018-09-17 13:53:35 -07:00
Ryan Macdonald 631f6cd55b More style fixes
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-08-31 14:30:17 -07:00
Ryan Macdonald 3516fd5019 Style fixes
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-08-31 14:29:09 -07:00
Ryan Macdonald 583c90e87c Add pass message for SBA and compliance tests
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-08-31 14:26:32 -07:00
Megan Wachs 4b29af433d Merge remote-tracking branch 'origin/riscv' into sba_tests 2018-08-31 09:02:55 -07:00
Megan Wachs 24513fe51f riscv-compliance: fix comment typo 2018-08-30 15:37:15 -07:00
Megan Wachs 7448f8780a riscv-compliance: fix whitespace 2018-08-30 11:30:14 -07:00
Megan Wachs 934440b80e riscv-compliance: incorporate review feedback 2018-08-30 11:26:05 -07:00
Tim Newsome 164415cfbe
Merge branch 'riscv' into sba_tests 2018-08-29 15:55:30 -07:00
Megan Wachs 34ee883aef Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebase 2018-08-29 15:47:54 -07:00
Tim Newsome b4b2ec7d2d
Add command to expose custom registers (#293)
* Added `riscv expose_custom` command.

Seems to work for reading. I need to do some more testing for writes, as
well as minor cleanup.

Change-Id: I85d5d00897d5da4add4a6643b538be37d31a016f

* Conform to OpenOCD style.

Change-Id: I40a316f06f418d2b63d9e11aea03ef51da8d8faf

* Free all the memory allocated by register init.

Change-Id: I04e35ab54613f99708cee85e41fef989079adefc

* Properly document `riscv expose_custom`.

Change-Id: Id78a02b7a00c161df80f11b521a306e0cf3d7478
2018-08-29 14:22:50 -07:00
Tim Newsome 684d7d6764
Remove unused variable. (#284)
Change-Id: Iedebce86b5d914ff612a4747ffdc6f776edca783
2018-08-20 12:42:30 -07:00
Tim Newsome ead2a595b8 Use work area instead of riscv-specific config
Per review requested at http://openocd.zylin.com/#/c/4578/3

Change-Id: I1a8117665d38844dc1479f33b4f9b7c8f9f101c8
2018-07-16 14:43:15 -07:00
Tim Newsome 2a6332f620 Update debug defines to match spec
The main difference is we need to deal with hartsello/hartselhi. (Note
that there's a compile-time limit to 16 harts, but that can be changed.)
My largest target has 4 harts, so I can't tell how well this really
works. But it doesn't break anything.

Fixes #240.

Change-Id: Ie1a2a789b5e00f55174994568749da1cf3a33b92
2018-06-06 13:43:35 -07:00
Tim Newsome ab7ab8a867
Merge pull request #261 from riscv/trigger_enum
Delay trigger enumeration until it's required.
2018-05-25 11:52:10 -07:00
Megan Wachs bdc4355493 Merge remote-tracking branch 'origin/trigger_enum' into riscv-compliance 2018-05-22 16:27:52 -07:00
Megan Wachs a0e811580a Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-22 16:27:29 -07:00
Tim Newsome b629bbeade Delay trigger enumeration until it's required.
This improves startup time, which is important when connecting to
simulators. One problem is that triggers that are set when the debugger
connects are not cleared until enumeration happens. Execution may halt
due to a trigger set by a previous debug session, which could confuse
the user. If this happens, triggers will be instantly enumerated, so it
will only happen once per session.

Change-Id: I3396f713f16980a8b74745a1672fe8b8a2d4abae
2018-05-22 13:07:25 -07:00
Tim Newsome 41c42bf2df Comment riscv_set_register, register_write_direct
Fixes #241

Change-Id: Ia199f15106a0bda465d3918d052ddd4d03655031
2018-05-17 18:01:00 -07:00
Megan Wachs 9a5a5c2dc9 Merge remote-tracking branch 'origin/reset-unexpected-check' into riscv-compliance 2018-05-16 22:29:45 -07:00
Megan Wachs 802c3b4003
riscv: remove unexpected check during reset
I'm not sure what this check is adding, and it causes problems for implementations that take some time to report that they are halted out of reset (e.g. by executing Debug ROM).
2018-05-16 22:25:38 -07:00
Megan Wachs efd7260972 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-14 07:31:25 -07:00
Tim Newsome 909c9d4ab2 Conform to OpenOCD style
Change-Id: I3954a8ac254b460560fa1414c5921777e4005645
2018-05-03 17:58:44 -07:00
Tim Newsome 487501e761 Merge branch 'riscv' into optimize
Change-Id: I2693eb05dee72acd2df5d8594c51e9da08ea1cc6
2018-05-03 16:02:59 -07:00
Tim Newsome 292180fb44
Merge pull request #246 from darius-bluespec/sysbus-bugfix
Bug fixes for system bus access
2018-05-01 14:12:48 -07:00
Darius Rad 31494f68a4 Properly retry system bus access if busy error was detected. 2018-05-01 11:45:24 -04:00
Darius Rad cb282e81bc Fix polling for system bus busy. 2018-05-01 11:45:24 -04:00
Tim Newsome b62c014bdc Merge branch 'riscv' into notice_reset 2018-04-30 13:36:06 -07:00
Ryan Macdonald 0ed96e80d3 Fix more style issues
Signed-off-by: Ryan Macdonald <rmac@sifive.com>
2018-04-24 14:15:30 -07:00
Ryan Macdonald 9089854b84 Code cleanup from feedback. 2018-04-24 14:01:21 -07:00