Commit Graph

9153 Commits

Author SHA1 Message Date
Kevin Vermilion ecc2f4a694 at91samd: Add flash programming support for SAMC2?N* parts
Added id, name, flash size and RAM size for following parts to samc20_parts[]:
SAMC20N18A
SAMC20N17A
And the following to samc21_parts[]:
SAMC21N18A
SAMC21N17A

Change-Id: Ie8cf1c531a60bfaed6e814d436d232afb89dae3f
Signed-off-by: Kevin Vermilion <kevin.vermilion@gmail.com>
Reviewed-on: http://openocd.zylin.com/4880
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-02-07 08:02:10 +00:00
Jean-Christian de Rivaz 740c3ec238 target start_algorithm: Don't copy the IN mem_params fix uninitialised value.
Fix the write only out params TODO on armv7m.c
Fix conditional move depends on uninitialised value.
It was detected while programming a LPC8Nxx with a FTDI adapter.
valgrind --leak-check=full --show-leak-kinds=all --track-origins=yes
[...]
==8696== Conditional jump or move depends on uninitialised value(s)
==8696==    at 0x16E4D3: buf_set_u32 (binarybuffer.h:52)
==8696==    by 0x16E4D3: ftdi_swd_queue_cmd (ftdi.c:1206)
==8696==    by 0x18D76D: swd_queue_ap_write (adi_v5_swd.c:271)
==8696==    by 0x18E33B: dap_queue_ap_write (arm_adi_v5.h:382)
==8696==    by 0x18E33B: mem_ap_write (arm_adi_v5.c:420)
==8696==    by 0x197CD9: target_write_buffer_default (target.c:2176)
==8696==    by 0x2464B3: armv7m_start_algorithm (armv7m.c:383)
==8696==    by 0x246AEB: armv7m_run_algorithm (armv7m.c:330)
==8696==    by 0x19D846: target_run_algorithm (target.c:814)
==8696==    by 0x1DF3A6: lpc2000_iap_call.isra.3 (lpc2000.c:818)
==8696==    by 0x1E0CF6: lpc2000_erase (lpc2000.c:992)
==8696==    by 0x185BDF: flash_driver_erase (core.c:44)
==8696==    by 0x18650D: flash_iterate_address_range_inner (core.c:541)
==8696==    by 0x18650D: flash_iterate_address_range (core.c:567)
==8696==    by 0x18732F: flash_erase_address_range (core.c:584)
==8696==    by 0x18732F: flash_write_unlock (core.c:928)
==8696==  Uninitialised value was created by a heap allocation
==8696==    at 0x4C2BBAF: malloc (vg_replace_malloc.c:299)
==8696==    by 0x220EF9: init_mem_param (algorithm.c:30)
==8696==    by 0x1DF247: lpc2000_iap_call.isra.3 (lpc2000.c:777)
==8696==    by 0x1E0CF6: lpc2000_erase (lpc2000.c:992)
==8696==    by 0x185BDF: flash_driver_erase (core.c:44)
==8696==    by 0x18650D: flash_iterate_address_range_inner (core.c:541)
==8696==    by 0x18650D: flash_iterate_address_range (core.c:567)
==8696==    by 0x18732F: flash_erase_address_range (core.c:584)
==8696==    by 0x18732F: flash_write_unlock (core.c:928)
==8696==    by 0x18ACDF: handle_flash_write_image_command (tcl.c:457)
==8696==    by 0x1B7D99: run_command (command.c:623)
==8696==    by 0x1B7D99: script_command_run (command.c:208)
==8696==    by 0x1B7FD9: command_unknown (command.c:1033)
==8696==    by 0x2E2D37: JimInvokeCommand (jim.c:10364)
==8696==    by 0x2E3865: Jim_EvalObj (jim.c:10814)
==8696==
==8696== Conditional jump or move depends on uninitialised value(s)
==8696==    at 0x16E506: buf_set_u32 (binarybuffer.h:52)
==8696==    by 0x16E506: ftdi_swd_queue_cmd (ftdi.c:1207)
==8696==    by 0x18D76D: swd_queue_ap_write (adi_v5_swd.c:271)
==8696==    by 0x18E33B: dap_queue_ap_write (arm_adi_v5.h:382)
==8696==    by 0x18E33B: mem_ap_write (arm_adi_v5.c:420)
==8696==    by 0x197CD9: target_write_buffer_default (target.c:2176)
==8696==    by 0x2464B3: armv7m_start_algorithm (armv7m.c:383)
==8696==    by 0x246AEB: armv7m_run_algorithm (armv7m.c:330)
==8696==    by 0x19D846: target_run_algorithm (target.c:814)
==8696==    by 0x1DF3A6: lpc2000_iap_call.isra.3 (lpc2000.c:818)
==8696==    by 0x1E0CF6: lpc2000_erase (lpc2000.c:992)
==8696==    by 0x185BDF: flash_driver_erase (core.c:44)
==8696==    by 0x18650D: flash_iterate_address_range_inner (core.c:541)
==8696==    by 0x18650D: flash_iterate_address_range (core.c:567)
==8696==    by 0x18732F: flash_erase_address_range (core.c:584)
==8696==    by 0x18732F: flash_write_unlock (core.c:928)
==8696==  Uninitialised value was created by a heap allocation
==8696==    at 0x4C2BBAF: malloc (vg_replace_malloc.c:299)
==8696==    by 0x220EF9: init_mem_param (algorithm.c:30)
==8696==    by 0x1DF247: lpc2000_iap_call.isra.3 (lpc2000.c:777)
==8696==    by 0x1E0CF6: lpc2000_erase (lpc2000.c:992)
==8696==    by 0x185BDF: flash_driver_erase (core.c:44)
==8696==    by 0x18650D: flash_iterate_address_range_inner (core.c:541)
==8696==    by 0x18650D: flash_iterate_address_range (core.c:567)
==8696==    by 0x18732F: flash_erase_address_range (core.c:584)
==8696==    by 0x18732F: flash_write_unlock (core.c:928)
==8696==    by 0x18ACDF: handle_flash_write_image_command (tcl.c:457)
==8696==    by 0x1B7D99: run_command (command.c:623)
==8696==    by 0x1B7D99: script_command_run (command.c:208)
==8696==    by 0x1B7FD9: command_unknown (command.c:1033)
==8696==    by 0x2E2D37: JimInvokeCommand (jim.c:10364)
==8696==    by 0x2E3865: Jim_EvalObj (jim.c:10814)

Change-Id: I50f9a8c4516b686cf62ac3c76f47c53465e949da
Signed-off-by: Jean-Christian de Rivaz <jcamdr70@gmail.com>
Reviewed-on: http://openocd.zylin.com/4811
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-02-07 08:01:25 +00:00
Jan Vojtech 9f576d3f48 flash/nor/stm32f1x: Ability to change user option bytes.
Adds ability to change the user data in STM32F1x/STM32F3x MCU's option byte.
Since OpenOCD prints the content of user data in option byte registers, it
is seems logical to also provide a way how to change this data.

Change-Id: Ie6cb756b4f11b5c6dabd34bc89434a358eb758ff
Signed-off-by: Jan Vojtech <honza.vojtech@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4663
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2019-02-07 07:52:44 +00:00
Tomas Vanek 7a3eec2b4d target algo: do not write reg_param if direction is PARAM_IN
Without this change xxx_start_algorithm() writes all register
parameters no matter of their direction. It usually results
in writing of uninitialized reg_params[].value - possibly
reported by valgrind.

While on it fix the wrong parameter direction in
kinetis_disable_wdog_algo(). This bug did not have any
impact because of unconditional write of reg_params.

Change-Id: Ia9c6a7b37f77d5eb6e5f5463012dddd50471742b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4813
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-02-07 07:51:50 +00:00
Antonio Borneo 0d48104e03 drivers/imx_gpio: fix polarity of srst and trst
The comment above the function is correct, but the code set
the GPIO with wrong (reversed) polarity.

Change-Id: Ifd09688150d3d2018af73521e0da3926bb1b7f84
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4847
Tested-by: jenkins
Reviewed-by: Grzegorz Kostka <kostka.grzegorz@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-02-07 07:51:41 +00:00
Oleksij Rempel a1b308abd4 jtag: drivers: provide initial support for usb path filtering
With this patch drivers will be able to use usb path filtering.
The path format is identical to the format provided by linux kernel:
bus-port.port....
With this format it should be easier just to copy and paste
path found in dmesg.

Change-Id: I8bafa6fcb7a66ff68cc961a376f97f4f3dee35aa
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-on: http://openocd.zylin.com/4580
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-02-07 07:51:30 +00:00
Tomas Vanek deaf3d2641 flash/nor: flash driver and cfg for SAM E54, E53, E51 and D51
The new Microchip (former Atmel) series powered by Cortex-M4 looks
very similar to older M0+ powered SAM D2x at the first sight.
Unfortunately the new series differs a lot in important details.
NVMCTRL has different register addresses, moved important bits
and even changed binary command set. An universal driver for all SAM D/E
would be very complicated. That's why a new driver was derived.

Tested on Microchip SAM E54 Xplained Pro kit (board cfg included).

Adjusted for the restructured dap support.
Checked by valgrind and clang static analyzer.

Change-Id: I26c67047a552076f4b207b9b89285a53d69b4ca4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4272
Tested-by: jenkins
Reviewed-by: Andres Vahter <andres.vahter@gmail.com>
2019-02-05 17:45:18 +00:00
Tomas Vanek 346ce2f13f flash/nor/stm32f1x: use address instead of offset in stm32x_write_block()
stm32x_write_options() uses stm32x_write_block() at STM32_OB_RDP address.
The change eliminates subtracting bank->base (and later adding it back).

Change-Id: Icdd24afc7178b814be58e6033d4b93fdfb2d2a16
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4859
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
2019-02-04 10:26:47 +00:00
Tomas Vanek e978e53c77 flash/nor/stm32f1x: fix minor error messages
Change-Id: I1e9e62979c4629c8ba1d5ae89ca7392259969eb6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4858
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
2019-02-04 10:26:22 +00:00
Tomas Vanek 4b998cb5f5 cortex_m: fix stepping on FPB rev 1
Stepping in the maskisr auto mode sets breakpoint to step over interrupt
service tasks. If the device has FPB rev 1, setting hard breakpoint
is impossible on address over 0x1fffffff.

Use soft type breakpoint for adresses over 0x1fffffff if FPB is rev 1.
This may eventually fail if the code memory is not writeable, but there
is nothing to do in such case.

Change-Id: Ibdeeb506903a35d550b64f82c24c37a668de62b3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4857
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-02-04 10:25:44 +00:00
Guillaume Revaillot 5105e6037f flash/nor/at91samd: add samr34j18.
samr34/r35 combine SAML21 and SX1276 (lora transceiver). This one was found on
xplaned pro evaluation kit. Ids for other r34/r35 chips are apparently not yet
documented.

Change-Id: I4054dd56ea53c9bae8d17abd5a3e4e65e1b9c8b1
Signed-off-by: Guillaume Revaillot <g.revaillot@gmail.com>
Reviewed-on: http://openocd.zylin.com/4872
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-02-04 10:24:01 +00:00
Tim Newsome c554246177
Merge pull request #347 from riscv/hwthread
`-rtos hwthread` support
2019-01-31 12:20:34 -08:00
Tim Newsome 14327c1acf
Fix sending memory-map for 64-bit targets. (#348)
See #202. I don't have a proper target with >32-bit flash and memory
location, so I've been unable to properly test this. However, if I hack
the fespi driver to not do anything and run the 64-bit spike tests I can
see that the memory map OpenOCD sends now includes the full 64-bit
address space:
Debug: 3443 975 gdb_server.c:400 gdb_put_packet_inner(): sending packet
'$l<memory-map>
<memory type="ram" start="0x00000000" length="0x20000000"/>
<memory type="ram" start="0x20000000" length="0xffffffffe0000000"/>
</memory-map>

It will also do this when the target is 32-bit, but that doesn't seem to
have any ill effects on gdb.

Change-Id: I0fd070ab7366188ff0259d90386f5e1f6985ce21
2019-01-31 12:16:15 -08:00
Antonio Borneo 7a80a74e81 arm_adi_v5: rewrite dap_to_jtag and dap_to_swd
The functions dap_to_jtag() and dap_to_swd() have been introduced by
3ef9beb52c ("ADIv5 DAP ops switching to JTAG or SWD modes") in
arm_adi_v5.c by using the JTAG queue only.
Later, in 6f8b8593d6 ("ADIv5 transport support moves to separate
files") the functions has been moved in adi_v5_swd.c and adi_v5_jtag.c
but keeping the dependency from JTAG queue.
The functions does not work if the current transport is not JTAG.

Move back the functions in arm_adi_v5.c, replace the input parameter
"target" with "dap", use the transport to detect if the JTAG queue is
present, in case of SWD transport use the proper method, for other
transports report error.
Reuse the ADI v5 sequences already present in jtag/swd.h.
Also, OpenOCD does not support switching to another transport after
the initial selection, so do not change DAP's ops vector.

Change-Id: Ib681fbaa60cb342f732bc831eb92de25afa4e4db
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4852
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-30 14:29:10 +00:00
Matthias Welwarsky bda2d73718 aarch64: support for aarch32 ARM_MODE_SYS
Treat ARM_MODE_SYS like all other Aarch32 processor modes,
except for the special case of missing SPSR.

Change-Id: I60b21703659b264f552884cdc0f85fd45f7836de
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4494
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-30 09:01:59 +00:00
Tomas Vanek 7345801b69 target: do not allow 'target create' after init
A target created after init lacks target_init_one() call
and is not added to gdb targets.

Steps to reproduce:
- start OpenOCD with a dap target
- connect by telnet
 target create ap0.mem mem_ap -dap $_CHIPNAME.dap -ap-num 0
 reset

Segmentation fault is rised because target->check_reset is NULL.

Change-Id: I2a62f3b450e4db3005c7041a22fb8f952e68c3b6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4842
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-27 20:59:54 +00:00
Tomas Vanek 877cec20dc command: check command mode for native jim commands
The command mode was checked only for simple type of commands.
Native commands (handled by jim_handler) was treated as
they had mode COMMAND_ANY

Change-Id: Iab1d8cbb0b8c6f6b9f3cf942600432dec9a703ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4841
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-27 20:59:42 +00:00
Tomas Vanek d479020950 target/cortex_m: inform if an external reset occurs
Change-Id: I873e73012c44aac7af3b21b633bd096d8e299d07
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4840
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-27 20:59:13 +00:00
Tomas Vanek d0eb66f729 command: Log the failed command by full name
Commit 44009186cf added logging
of failed cmd name but it used c->name only. It might be confusing:

Debug: 244 105 command.c:644 run_command(): Command 'init' failed with error
 code -4
User : 245 106 command.c:711 command_run_line():
Debug: 246 107 command.c:644 run_command(): Command 'init' failed with error
 code -4

The command on line 244 is 'dap init'
Use full name of cmd including parents.

Change-Id: Iff131ce6454ef70b353ce1bc6d0a480b92820545
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4837
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Jean-Christian de Rivaz <jcamdr70@gmail.com>
2019-01-27 20:58:10 +00:00
Tomas Vanek d9cb5593cd hla_target: fix adapter_poll() to preserve TARGET_DEBUG_RUNNING state
Without this change TARGET_DEBUG_RUNNING changes to TARGET_RUNNING
after adapter_poll()

Change-Id: I1c965a43527b50fa723d78fb6eae56585a7ede03
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4820
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-27 20:58:03 +00:00
Antonio Borneo fc348bc086 command: initialize the command mode for every command
All the commands in OpenOCD have been inspected and have the
command mode initialize, apart for two of them.
This is not critical, because the uninitialized value (0) is
equivalent to the enum COMMAND_EXEC, that is also the correct
value for the two mentioned commands.

To keep the code consistent, initialize the command mode to
COMMAND_EXEC.

Change-Id: Iaf043364cbd1005418d787ed045a3ec653612382
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4861
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-27 11:45:01 +00:00
Peter Lawrence 8417a569fe tcl: Support for Analog Devices ADSP-SC58x / ADSP-SC584-EZBRD
The original script was broken by changes to the Cortex-A code.  The
recent introduction of the mem_ap target provided a new mechanism to
allow the script to be fixed.  This also adds an example board script
for the ADSP-SC584-EZBRD.

Change-Id: I36bc1ac6b6c036539f4175f1e65223ba10a35355
Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
Reviewed-on: http://openocd.zylin.com/4855
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-26 22:32:10 +00:00
Tim Newsome 220a97979f Use more compatible printf formatting.
Change-Id: I5d5b46f3e6c4f5abff1c0efa3ea8b4f589c1e635
2019-01-25 15:56:26 -08:00
Tim Newsome e186f62962 More cleanup.
Change-Id: I804bdcec23b69d77dfc376e23c6d1f29f99e7335
2019-01-25 15:31:42 -08:00
Tim Newsome 96df1db7b1 Remove debug statements.
Change-Id: If37bc883fea0b83740bfd6a7fcb2091db0ac61f0
2019-01-25 14:48:22 -08:00
Tim Newsome 49dd7ded87 Merge branch 'riscv' into hwthread 2019-01-25 14:17:32 -08:00
Tim Newsome 82cf37d36c Invalidate register cache on reset.
All tests pass with `-rtos hwthread` against spike32!

Change-Id: I9051259d2702c76b7c35aeffeac020a773e0597a
2019-01-25 13:11:06 -08:00
Tim Newsome b29215735c Properly clean up SMP watchpoints.
42/43 tests pass.

Change-Id: Ia800ffacf914742e8b9bdb1799ca3817856448a4
2019-01-25 09:19:33 -08:00
Tim Newsome afedcb337a WIP on hardware breakpoints.
This is messy, but contains at least some bugfixes.

39/43 tests pass now.

Change-Id: Ic9e8dad2a0ceb237e28c93906d1cd60876a5766d
2019-01-24 15:27:53 -08:00
Tim Newsome eb7af6cba0
Merge pull request #346 from riscv/dmactive
Move version check until after dmactive=1.
2019-01-24 12:28:06 -08:00
Antonio Borneo f63b519385 jtag: cmsis-dap: use macro SWJ_PIN_SRST in place of magic value
While connecting under reset, use the already defined macro
SWJ_PIN_SRST to assert the srst pin.

Change-Id: Icebed462c0fe8f8c15f6522dc56625aa580b8858
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4846
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-23 15:27:13 +00:00
Moritz Fischer 731dc36a67 rtos: Add RTOS task awareness for Chromium-EC
Add RTOS task awareness for Chromium-EC. Currently
only supports ARM Cortex-M0/M3/M4 based targets.

No new Clang Analyzer warnings.

Change-Id: Iea56fcb1be220e2437613922879b63d6e553703d
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: http://openocd.zylin.com/4685
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-23 15:27:01 +00:00
Jonathan McDowell d2fb461621 Correct ZynqMP configuration to be appropriately named
The xilinx_ultrascale.cfg target is actually the configuration for a
ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad
core A53. Update the filename/comments to reflect this, and include
the tap IDs for all known FPGA cores for this part.

Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4850
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-23 15:26:48 +00:00
Antonio Borneo 45b4998e93 arm_opcode: fix encoding of ARMv5 breakpoint instruction
The encoding of BKPT instruction is 0xE12###7#, where the four '#'
characters should be replaced by the 16 bits immediate value.
The macro uses an incorrect shift amount, thus the immediate value
is not properly coded and bits 20~23 of the opcode could get
corrupted.

Fixed by using the proper shift amount.

Change-Id: I32db8224ab57aad6d3b002f92f9f259056593675
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4854
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-23 15:26:39 +00:00
Antonio Borneo c2e18bfaea arm_adi_v5: fix and update sequences to spec IHI 0031E
Fix the SWD line reset sequence accordingly to Arm specification IHI
0031E that requires at least 2 idle clocks after the 50 clocks with
SWDIO high.
Fix the value of the activation code in the (currently unused)
sequence dormant-to-SWD.
Make each sequence's length multiple of 8, so it is compatible with
adapters that have such limitation (e.g. buspirate) and try to split
and comment each part of the sequence (when possible keep each part
byte aligned, inspired from commit 3ef9beb52c). This slightly
increases the sequence length but does not impact run-time
performance because these are rarely used sequences.
Add the missing sequence dormant-to-JTAG and JTAG-to-dormant, not
used yet.

On devices that implements the dormant state, IHI 0031E deprecates
the direct switching between SWD and JTAG, and recommends using a
transition through dormant. This is not implemented.

Change-Id: Iad18c0e736cfd9366be175d22658d664b0c61eab
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4851
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-23 15:26:28 +00:00
Tomas Vanek 418515b21e target/arm_dap: fix segmentation fault in 'dap info' cmd
'dap info' command fails hard on a hla target.

Change-Id: Ia188b1afe527e0ed64512d1bddadd507f978e40b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4860
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-23 15:25:53 +00:00
Tim Newsome 906635c4bd Move version check until after dmactive=1.
This should allow OpenOCD to work with targets where version is not
readable when dmactive=0, which is allowed by the spec.
2019-01-22 12:48:47 -08:00
Mirko Vogt 8896abbf07 nrf5: add nrf5 device definition for HWID 0x00E3
This hardware id is e.g. used by the Insight SiP ISP1507-AX.

Change-Id: I82568d292f9882372ab061d8e3e36906b0cc5882
Signed-off-by: Mirko Vogt <mirko.vogt@sensorberg.com>
Reviewed-on: http://openocd.zylin.com/4845
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2019-01-21 00:01:16 +00:00
Tim Newsome c296c62521 Halt all SMP harts on halt request.
38/45 tests pass.

Change-Id: Ia4fd523139c197020d9277be4bf5f92079520068
2019-01-18 13:18:15 -08:00
Tim Newsome 348f15315e Don't reset current thread id on single step.
Now passing 36/45 tests.

Change-Id: I244b045f84397b058cf526e3bff238cb05d8ad06
2019-01-18 11:34:26 -08:00
Tim Newsome c1ef5f61c3 Fix reading of non-general registers for hwthread
Previously the code made the assumption (which is valid for conventional
RTOSs) that special registers (e.g. CSRs) are the same across threads.

26/45 tests pass.

Change-Id: Ibb3398790d7354a995d506772375d869f608f1f0
2019-01-17 15:01:47 -08:00
Tarek BOCHKATI d140fb27c6 cortex_m: fix bug in poll() machine state (external resume awareness)
This patch covers the fact that cortex_m could be resumed externally by
Cross Trigger Interface or by direct write to DHSCR ...

To reproduce:
 - halt the target
 - then run the core through DHCSR (mww 0xe000edf0 0xa05f0001)
 => this resumes the core, but target state in OpenOCD remains HALTED.

Change-Id: Ifa1ae18645bfeb863acc78a039bbf04873fd78fe
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/4817
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-16 10:53:24 +00:00
Tarek BOCHKATI 63aa917015 cortex_a_poll: minor code factorization to enhance readability
cortex_a_debug_entry and update_halt_gdb are called in two consecutive
conditions which are complementary, so externalizing the common code
makes the conditions' body lighter

With the removal of LOG_DEBUG(" ") since it does not look too informative

Change-Id: I0c54e413619576bb3af164f2dcf256c5a862c5fd
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/4832
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2019-01-16 10:52:43 +00:00
Severin Junker c915e70568 at91samd: added SAM-DA1 parts
Change-Id: I1b206461052ee1897432e379505fdf95372a9e24
Signed-off-by: Severin Junker <s.junker@cartelsol.com>
Reviewed-on: http://openocd.zylin.com/4835
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-16 10:52:06 +00:00
Antonio Borneo c4a7a62262 helper/command: check for malloc failure in __command_name
If malloc fails in __command_name, the following strcpy will
segfault, thus preventing __command_name to return.
The actual calls to command_name() implement the correct check
for the NULL pointer, but propagate error -ENOMEM, that is not
an error value coherent within OpenOCD. Plus, in one case it
overwrites an already detected error.

Check the pointer returned by malloc and, in case of failure,
issue an error message and return the NULL pointer.
Let the caller of command_name() to keep the already detected
error or to return ERROR_FAIL in case of end of memory.

Change-Id: I151a24569409777dd5bc09a3daf5dba2b8e2829b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4838
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-16 10:51:28 +00:00
Tomas Vanek c0ec54d8ae target/stm8: add missing destroy_reg_param()
Change-Id: Ibd8a423a4400226790cfbb9a6f113b7ea762c436
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4814
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ake Rehnman <ake.rehnman@gmail.com>
2019-01-14 08:46:36 +00:00
Antonio Borneo 87adca299d drivers/sysfsgpio: fix usage messages
The notation "(tck tms tdi tdo)* " is incorrect, because it means the
quadruple of gpio can be repeated on the command-line.
The correct syntax of the command requires instead to provide either
all the four gpio numbers (in order to set the values) or to pass an
empty command-line (to dump the values previously set).

Change the .usage field to "[tck tms tdi tdo]".
Change similarly the corresponding .usage field for SWD command.
Add the .usage field for the commands that individually set each gpio.

Change-Id: If5b3c618097b71dfe7fcf988fb3c1499ae03a6d5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4833
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-14 08:45:35 +00:00
Tim Newsome c84d56debc rtos support to write registers on current thread
I don't understand how it was ever possible to change the registers on a
thread that's not the current active one when a halt happened. Really
instead of the RTOS tracking what the currently selected thread is, it
would make more sense to have gdb_server do that and simply pass it
along in every call to the RTOS layer.

Now MulticoreRegTest passes.

Change-Id: I399b9b2b05a147aa6b41463714ed3a39534b1fc8
2019-01-11 13:53:53 -08:00
Tim Newsome 31ea7037b3 Add flash support for SiFive's Freedom E platforms
Valgrind and Clang Static Analyzer have no complaints about this change.

Change-Id: I7757615ec52448372bdc57729cdf97c7016d97e8
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4656
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-11 19:50:09 +00:00
Tim Newsome 1599853032
Merge pull request #345 from darius-bluespec/set_ir
Add 'riscv set_ir' command to set IR value for JTAG registers.
2019-01-11 08:44:59 -08:00