* riscv: Fix bugs. Do not touch SATP if there is no MMU.
In some platform, there is no SATP register at all.
OpenOCD will report unexpected errors if SATP is unreadable.
So, use 'riscv_enable_virtual' to guard SATP access.
* riscv: fix format typo.
Fix memory access on 64-bit targets with no progbuf and sba that
supports 32-bit accesses but not 64-bit accesses. Bug was introduced in #419.
This fixes https://github.com/riscv/riscv-tests/issues/217.
Change-Id: Ib5ddf9886b77e3d58fe1d891b560ad03d5a46da1
* fix for batch scans not honoring presence of BSCAN tunnel
* fix formatting to placate checkpatch
* replace DIM with ARRAY_SIZE
* Refactor code that adds a bscan tunneled scan.
* Move bscan tunnel context to the batch structure, and in array
form, one per scan
* adjust code that was inconsistent with project code formatting standards
* 64-bit progbuf memory reads work.
Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399
* 64-bit writes work.
Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23
* Let targets indicate number of supported data bits.
This is used by the default memory read/write functions when creating an
aligned block.
I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.
Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b
* Make mingw32 happy.
Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
* Align algorithm stack to XLEN.
This fixes algorithm timeout on RV64 targets.
Also improve debug information in various places.
Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d
* Compile 32-bit RISC-V algorithms for RV32E.
Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa
* Remove debug code.
Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b
* Dump start of gdb packets escaping non-printable.
Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915
* Propagate flash programming errors.
Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7
* Improve debug messaging.
Change-Id: I47ac3518f3b241986c677824864102936100adf6
* Add debug output to flash image.
This is helpful when you're debugging the flash algorithm itself, and a
nop when running it through OpenOCD.
Change-Id: Id44c6498c288872cc2cec79044116ac38198c572
* Make timeout depend on how much data is written.
Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e
* Fix issi erase commands.
This is required to flash HiFive Unleashed.
Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10
* Fix running algorithm on multicore `-rtos riscv`.
The bug was that poll() might change the currently selected hart, and in
that case we'd access registers on that other hart after the algorithm
is finished.
Change-Id: I140431898285cf471b372139cef2378ab4879377
* Make fespi flash algorithm debugging optional.
Also add a scheme that allows you to see the stack trace of where a
failure occurred if debugging is enabled.
Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
* Clear cmderr by writing all ones.
This should have been part of #389.
Change-Id: Ie40e95fdd904af65c53d1f5de7c8464b27038ec0
* Don't update reg cache in register_write_direct().
This function explicitly bypasses any caches.
Change-Id: Ie3c9a1163e870f80c0ed75b74495079c527663e9
* Use only one hart to run algorithm.
Fixes a bug with `-rtos hwthread` where all harts would run when running
a flash/CRC algorithm, which would probably ruin flashing, and was
unexpectedly changing registers on other harts for the CRC algorithm.
Change-Id: Ia2f600624f4c8d4cab319861fef2c14722f08b53
* add opcode for csrrsi and csrrci
* enable MMU while reading/writing memory using progbuf
* fix style issues
* keep old behavior for progbufsize<4, perform r/w/csr only when necessary
* do not pass progbufsize, only write mstatus if changed
* add config option to enable virtualization feature
* throw error if virt enabled but unavaliable, outsource modify_privilege
* support virtualization for read_memory_progbuf_one
* Make resume order configurable.
This is a customer requirement. Using this option is discouraged.
Change-Id: I520ec19cc23d7837cb8576f69dadf2b922fa2628
* Fix style.
Change-Id: If8e515984c92ce8df52aa69e87abde023897409f
* Make mingw32-gcc happy.
Change-Id: I39852aedec293294b2b2638ab2cc45494fe77beb
* WIP, rewrite of flash algorithm.
Just put all the flashing logic into the algorithm, instead of using an
intermediate format. This should reduce total data written while
flashing by about 9%, and also makes the code much simpler.
Change-Id: I807e60c8ab4f9f376cceaecdbbd10a2326be1c79
* New algorithm works.
Speeds up Arty flashing another 9%.
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 86.784538s (25.074 KiB/s)
verified 2192012 bytes in 6.693336s (319.816 KiB/s)
8.66user 13.03system 1:33.91elapsed 23%CPU (0avgtext+0avgdata 12272maxresident)k
Change-Id: Ie55c5250d667251be141cb32b144bbcf3713fce4
* Fix whitespace.
Change-Id: I338d518fa11a108efb530ffe75a2030619457a0b
* Don't reserve so much stack space.
Also properly check XLEN in riscv_wrapper.S.
Change-Id: Ifa0301f3ea80f648fb8a6d6b6c8bf39f386fe4a6
* In theory support RV32E.
Change-Id: Icfe2a40976ae3161f2324e5bb586915aa4c4c7ee
* In theory support RV32E.
At least very basic tests pass.
Change-Id: Ia42e28a3fa020b3e52c92109392c46d009330355
* Fix cut and paste bug.
Change-Id: Ibfea68b39d706f59a8c3aa8153bb4db9803958c6
* Add hacks to make RV32E work with gdb.
gdb currently requires all 32 GPRs to be present, even on RV32E targets.
Once gdb is fixed these hacks can be removed.
Change-Id: Idcde648de2ca1a3f5b31315aab35fac86580af2c
* Cache program buffer writes.
Speeds up flash program by 3%, flash verify by 2%.
Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a
* Remove nop from batch reads.
program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287
KiB/s, verify @ 23.148 KiB/s originally).
Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935
* Use "algorithm" to compute CRC on RISC-V targets.
Use the C compiler to generate the algorithm code. It's better at
assembly than I am. We need separate RV32 and RV64 binaries to handle
shift instructions. I used the code from gdb (libiberty really) because
it returns the correct result. I'm not sure if the table is worth it
since we do have to save/download/restore more bytes now.
riscv_run_algorithm() now properly saves and reads back all registers
used for parameters. It also doesn't check final_pc if exit_point is 0.
Using gdb means I don't know the exact address where the code will end.
Small target.[ch] change to be able to run algorithms at 64-bit
addresses.
Flashing an arty board now:
```
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s)
verified 2192012 bytes in 7.037476s (304.177 KiB/s)
9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k
```
Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190
* Clean up formatting.
Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
* Inverted Frame to Pseudo Tap for Simpler Hardware to Decode
Given the variable supported message length , a prefix decoding approach is significantly simpler for a pseudo tap architecture with a shift reg of len = max len of packet. This prefix coding packet also makes the message len field redundant , as that is implict in ir_len and the ir selected.
* style patch
* non-conflict with original
* style patch
* style patch
* requested changes
* style-patch
To prepare for handling TCL return values consistently, all calls
to command_print/command_print_sameline should switch to CMD as
first parameter.
Change prototype of command_print() and command_print_sameline()
to pass CMD instead of CMD_CTX.
Since the first parameter is currently not used, the change can be
done though scripts without manual coding.
This patch is created using the command:
sed -i PATTERN $(find src/ doc/ -type f)
with all the following patters:
's/\(command_print(cmd\)->ctx,/\1,/'
's/\(command_print(CMD\)_CTX,/\1,/'
's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/'
's/\(command_print_sameline(cmd\)->ctx,/\1,/'
's/\(command_print_sameline(CMD\)_CTX,/\1,/'
's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/'
This change is inspired by http://openocd.zylin.com/1815 from Paul
Fertser but is now done through scripting.
Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5081
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested with SiFive HiFive1 development board.
Change-Id: I96a9a528057fcf9fc54d3da46a672d2cd54c3d5f
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4885
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
While initializing struct command_registration, the field's name "name"
is not specified, thus relying on the fact that it is the first field
declared in the struct and it's initialization value can be listed as
the first one.
Be coherent in the struct initialization and always use the field's
name.
Change-Id: Iefaeb15cc051db9f1e0f0140fe2f231b45f5bb12
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5013
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
* Remove unnecessary 0.11 code.
Don't need need_strict_step anymore now that we have
riscv_hit_watchpoint().
Don't need 32-bit warning in riscv011_resume() now that address is a
target_address_t.
Change-Id: I375c023a7ec9f62d80b037ddb64d14526ba0a3dc
* WIP little refactor working towards hasel support.
Change-Id: Ie0b8dfd9e5ae2e36613fa00e14c3cd32749141bf
* More refactoring.
Change-Id: I083387c2ecff78ddfea3ed5078444732d77b909b
* More refactoring.
Change-Id: Icea1308499492da51354f89e1529353e8385f3a1
* Starting to work towards actual hasel changes.
Change-Id: If0df05ffa66cc58400b4855f9630a8b1bae3030e
* Implement simultaneous resume using hasel.
Change-Id: I97971d7564fdb159d2052393c8b82a2ffaa8833f
* Add support back for targets that don't have hasel.
Change-Id: I6d5439f0615d5d5333127d280e4f2642649a119a
* Make hasel work with >32 harts.
Change-Id: I3c55009d48bfc5dd62e3341df4e4bd21df2fe44f
This represents months of continuing RISC-V work, with too many changes
to list individually. Some improvements:
* Fixed memory leaks.
* Better handling of dbus timeouts.
* Add `riscv expose_custom` command.
* Somewhat deal with cache coherency.
* Deal with more timeouts during block memory accesses.
* Basic debug compliance test.
* Tell gdb which watchpoint hit.
* SMP support for use with -rtos hwthread
* Add `riscv set_ir`
Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4922
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Targets can use this to expose how many address bits there are.
gdb_server uses this to send gdb the appropriate upper limit in the
memory-map. (Before this change the upper limit would only be correct
for 32-bit targets.)
Change-Id: Idb0933255ed53951fcfb05e040674bcdf19441e1
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4947
Tested-by: jenkins
Reviewed-by: Peter Mamonov <pmamonov@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
* Implement riscv_get_thread_reg().
This is necessary because riscv_get_gdb_reg_list() now reads all
registers, which ended up causing `-rtos riscv` to read all registers
whenever one was requested (because the register cache is wiped every
time we switch to a different hart).
CustomRegisterTest went from 1329s to 106s.
Change-Id: I8e9918b7a532d44bca927f67aae5ac34954a8d32
* Also implement riscv_set_reg().
Now all the `-rtos riscv` tests pass again, at regular speed.
Change-Id: I55164224672d9dcc9eb4d1184b47258ff3c2cff1
* Better error messages.
Change-Id: I4125f9a54750d9d0ee22c4fa84b9dd3f5af203f5
* Add target_get_gdb_reg_list_noread().
Being explicit about what's expected gets `-rtos riscv` back to `-rtos
hwthread` time.
Change-Id: I6e57390c2fe79b5e6799bfda980d89697e2e29f7
* Revert a change I made that has no effect.
I don't understand exactly what all this test protects against, and I
shouldn't change it unless I do.
Change-Id: Ib329d4e34d65d2b38559b89b7afb3678f439ad2c
Without this change xxx_start_algorithm() writes all register
parameters no matter of their direction. It usually results
in writing of uninitialized reg_params[].value - possibly
reported by valgrind.
While on it fix the wrong parameter direction in
kinetis_disable_wdog_algo(). This bug did not have any
impact because of unconditional write of reg_params.
Change-Id: Ia9c6a7b37f77d5eb6e5f5463012dddd50471742b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4813
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Previously the code made the assumption (which is valid for conventional
RTOSs) that special registers (e.g. CSRs) are the same across threads.
26/45 tests pass.
Change-Id: Ibb3398790d7354a995d506772375d869f608f1f0
* Changed logging level
* Added logging statement
* Removed halt event when attaching to target
* Extended some packet handling
* Extended handling of rtos_hart_id and clearing of register cache
* Extended execute_fence to handle all harts
* Removing logging statement again
* Updated according to review comments
* Forgot to re-add the return statement
* Was removing too much for the if statement to work
* This needs to >= 3 now to handle both a fence and a fence.i