Commit Graph

254 Commits

Author SHA1 Message Date
Tim Newsome 23a0ce22cf Reading v* registers appears to work.
Can't really test it though, because gdb doesn't print them right.

Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5
2020-01-24 14:52:19 -08:00
Tim Newsome 9e80ab1f85 WIP
Change-Id: I0264a73b7f7d2ce89cc0b80692dbf81d9cdcc2fd
2020-01-20 15:03:22 -08:00
Tim Newsome 8b8db033ee
Upcast mask value to work with 64-bit physical (#436)
Change-Id: I00f0d2a3c79a431e1aa49c7478fa6c17e2fa5256
2020-01-06 16:57:15 -08:00
Hsiangkai 2c3f099b73 Fix bugs. Do not touch SATP if there is no MMU. (#435)
* riscv: Fix bugs. Do not touch SATP if there is no MMU.

In some platform, there is no SATP register at all.
OpenOCD will report unexpected errors if SATP is unreadable.
So, use 'riscv_enable_virtual' to guard SATP access.

* riscv: fix format typo.
2019-12-31 11:27:22 -08:00
Hsiangkai 9886f77374 riscv: translate virtual address to physical address. (#425)
* riscv: translate virtual address to physical address.

* riscv: fix formatting errors.

* riscv: fix build errors.

* riscv: Remove redundant command for virtual address access.

* Revert "riscv: Remove redundant command for virtual address access."

This reverts commit 990d09eac3.

* riscv: Change command disable_virt2phys  to set_enable_virt2phys

1. Avoid double negative logic to make users easy to use.
2. Add document about new comomand 'riscv set_enable_virt2phys on|off'
2019-12-10 12:18:03 -08:00
Tim Newsome 780d8e4d3e
Remove unused data structure. (#431)
Saves 1.4MiB of RAM too, with just 1 hart configured.

Change-Id: I68d8c003a67c280b62ff6c9285ac6f54865f99f2
2019-12-04 16:23:22 -08:00
Tim Newsome de00906ebd
Fix memory access on some targets. (#428)
Fix memory access on 64-bit targets with no progbuf and sba that
supports 32-bit accesses but not 64-bit accesses. Bug was introduced in #419.

This fixes https://github.com/riscv/riscv-tests/issues/217.

Change-Id: Ib5ddf9886b77e3d58fe1d891b560ad03d5a46da1
2019-11-22 11:37:46 -08:00
Greg Savin b7bd3f8d47 BSCAN batch fix (#422)
* fix for batch scans not honoring presence of BSCAN tunnel

* fix formatting to placate checkpatch

* replace DIM with ARRAY_SIZE

* Refactor code that adds a bscan tunneled scan.

* Move bscan tunnel context to the batch structure, and in array
form, one per scan

* adjust code that was inconsistent with project code formatting standards
2019-11-12 09:00:35 -08:00
Tim Newsome f93ede5401
Add support for 64-bit memory reads/writes (#419)
* 64-bit progbuf memory reads work.

Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399

* 64-bit writes work.

Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23

* Let targets indicate number of supported data bits.

This is used by the default memory read/write functions when creating an
aligned block.

I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.

Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b

* Make mingw32 happy.

Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
2019-11-04 11:04:30 -08:00
Tim Newsome 20804cb4d2
pmpcfg[13] only exist on RV32. (#416)
Change-Id: I38f10d34b163eb7d0bf44b5717bbb027b0e43e76
2019-10-23 11:37:51 -07:00
Tim Newsome 9aac179cf2 Merge branch 'master' into from_upstream
Change-Id: I036350ee06aa396344fb8a80c7dba148ec24c9c8
2019-09-27 12:07:00 -07:00
Tim Newsome 274be9587f
Fix flashing HiFive Unleashed (#402)
* Align algorithm stack to XLEN.

This fixes algorithm timeout on RV64 targets.
Also improve debug information in various places.

Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d

* Compile 32-bit RISC-V algorithms for RV32E.

Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa

* Remove debug code.

Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b

* Dump start of gdb packets escaping non-printable.

Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915

* Propagate flash programming errors.

Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7

* Improve debug messaging.

Change-Id: I47ac3518f3b241986c677824864102936100adf6

* Add debug output to flash image.

This is helpful when you're debugging the flash algorithm itself, and a
nop when running it through OpenOCD.

Change-Id: Id44c6498c288872cc2cec79044116ac38198c572

* Make timeout depend on how much data is written.

Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e

* Fix issi erase commands.

This is required to flash HiFive Unleashed.

Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10

* Fix running algorithm on multicore `-rtos riscv`.

The bug was that poll() might change the currently selected hart, and in
that case we'd access registers on that other hart after the algorithm
is finished.

Change-Id: I140431898285cf471b372139cef2378ab4879377

* Make fespi flash algorithm debugging optional.

Also add a scheme that allows you to see the stack trace of where a
failure occurred if debugging is enabled.

Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
2019-09-09 12:01:17 -07:00
Tim Newsome 5173ddf75e
Use only one hart to run algorithm. (#396)
* Clear cmderr by writing all ones.

This should have been part of #389.

Change-Id: Ie40e95fdd904af65c53d1f5de7c8464b27038ec0

* Don't update reg cache in register_write_direct().

This function explicitly bypasses any caches.

Change-Id: Ie3c9a1163e870f80c0ed75b74495079c527663e9

* Use only one hart to run algorithm.

Fixes a bug with `-rtos hwthread` where all harts would run when running
a flash/CRC algorithm, which would probably ruin flashing, and was
unexpectedly changing registers on other harts for the CRC algorithm.

Change-Id: Ia2f600624f4c8d4cab319861fef2c14722f08b53
2019-08-26 11:24:29 -07:00
Nils Wistoff 239a515a9c Access memory through the scope of current privilege level (#386)
* add opcode for csrrsi and csrrci

* enable MMU while reading/writing memory using progbuf

* fix style issues

* keep old behavior for progbufsize<4, perform r/w/csr only when necessary

* do not pass progbufsize, only write mstatus if changed

* add config option to enable virtualization feature

* throw error if virt enabled but unavaliable, outsource modify_privilege

* support virtualization for read_memory_progbuf_one
2019-07-18 13:15:28 -07:00
Tim Newsome 6983eda0e9
Make resume order configurable. (#388)
* Make resume order configurable.

This is a customer requirement. Using this option is discouraged.

Change-Id: I520ec19cc23d7837cb8576f69dadf2b922fa2628

* Fix style.

Change-Id: If8e515984c92ce8df52aa69e87abde023897409f

* Make mingw32-gcc happy.

Change-Id: I39852aedec293294b2b2638ab2cc45494fe77beb
2019-07-15 10:32:28 -07:00
Tim Newsome c5dee66a71
Redo fespi flash algorithm (#384)
* WIP, rewrite of flash algorithm.

Just put all the flashing logic into the algorithm, instead of using an
intermediate format. This should reduce total data written while
flashing by about 9%, and also makes the code much simpler.

Change-Id: I807e60c8ab4f9f376cceaecdbbd10a2326be1c79

* New algorithm works.

Speeds up Arty flashing another 9%.

wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 86.784538s (25.074 KiB/s)
verified 2192012 bytes in 6.693336s (319.816 KiB/s)
8.66user 13.03system 1:33.91elapsed 23%CPU (0avgtext+0avgdata 12272maxresident)k

Change-Id: Ie55c5250d667251be141cb32b144bbcf3713fce4

* Fix whitespace.

Change-Id: I338d518fa11a108efb530ffe75a2030619457a0b

* Don't reserve so much stack space.

Also properly check XLEN in riscv_wrapper.S.

Change-Id: Ifa0301f3ea80f648fb8a6d6b6c8bf39f386fe4a6
2019-07-09 10:05:07 -07:00
Tim Newsome 8f2d2c27e8
RV32E support (#387)
* In theory support RV32E.

Change-Id: Icfe2a40976ae3161f2324e5bb586915aa4c4c7ee

* In theory support RV32E.

At least very basic tests pass.

Change-Id: Ia42e28a3fa020b3e52c92109392c46d009330355

* Fix cut and paste bug.

Change-Id: Ibfea68b39d706f59a8c3aa8153bb4db9803958c6

* Add hacks to make RV32E work with gdb.

gdb currently requires all 32 GPRs to be present, even on RV32E targets.
Once gdb is fixed these hacks can be removed.

Change-Id: Idcde648de2ca1a3f5b31315aab35fac86580af2c
2019-07-08 12:26:01 -07:00
Tim Newsome bb03f79bde
Improve block read and checksum speed (#381)
* Cache program buffer writes.

Speeds up flash program by 3%, flash verify by 2%.

Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a

* Remove nop from batch reads.

program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287
KiB/s, verify @ 23.148 KiB/s originally).

Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935

* Use "algorithm" to compute CRC on RISC-V targets.

Use the C compiler to generate the algorithm code. It's better at
assembly than I am. We need separate RV32 and RV64 binaries to handle
shift instructions. I used the code from gdb (libiberty really) because
it returns the correct result. I'm not sure if the table is worth it
since we do have to save/download/restore more bytes now.

riscv_run_algorithm() now properly saves and reads back all registers
used for parameters. It also doesn't check final_pc if exit_point is 0.
Using gdb means I don't know the exact address where the code will end.

Small target.[ch] change to be able to run algorithms at 64-bit
addresses.

Flashing an arty board now:
```
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s)
verified 2192012 bytes in 7.037476s (304.177 KiB/s)
9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k
```

Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190

* Clean up formatting.

Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
2019-06-19 10:56:37 -07:00
Paul George fd9c54b1fe Inverted Frame to Pseudo Tap for Simpler Hardware to Decode DR (#373)
* Inverted Frame to Pseudo Tap for Simpler Hardware to Decode

Given the variable supported message length , a prefix  decoding approach is significantly simpler for a pseudo tap architecture with a shift reg of len =  max len of packet. This prefix coding packet also makes the message len field redundant , as that is implict in ir_len and the ir selected.

* style patch

* non-conflict with original

* style patch

* style patch

* requested changes

* style-patch
2019-06-10 13:33:50 -07:00
Antonio Borneo 6cb5ba6f11 helper/command: change prototype of command_print/command_print_sameline
To prepare for handling TCL return values consistently, all calls
to command_print/command_print_sameline should switch to CMD as
first parameter.

Change prototype of command_print() and command_print_sameline()
to pass CMD instead of CMD_CTX.
Since the first parameter is currently not used, the change can be
done though scripts without manual coding.
This patch is created using the command:
	sed -i PATTERN $(find src/ doc/ -type f)
with all the following patters:
	's/\(command_print(cmd\)->ctx,/\1,/'
	's/\(command_print(CMD\)_CTX,/\1,/'
	's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/'
	's/\(command_print_sameline(cmd\)->ctx,/\1,/'
	's/\(command_print_sameline(CMD\)_CTX,/\1,/'
	's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/'

This change is inspired by http://openocd.zylin.com/1815 from Paul
Fertser but is now done through scripting.

Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5081
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-05-14 19:37:11 +01:00
Tim Newsome 5cb2f200f8
Simultaneous halt (#372)
* WIP

Change-Id: I4f50dced77e9ded4a58ab152824a841a73bc0dc1

* riscv_halt() only halt harts that are running.

Progress towards simultaneous halt.

Change-Id: I749b6d9ba5e77aa7aca4342c7af841312b78be0e

* -rtos riscv passes.

But dual gdb is failing again.

Change-Id: I1747ba42ce3f3062f6e8c28a75ac40e17f80e980

* Dual gdb works again.

-rtos riscv still works.

Change-Id: Idddddda79e5918b26e181384def1a305ecceced2

* -rtos hwthread almost completely works.

Change-Id: I845feb0bd93484e28ca8620f4760c234d4ce5310

* Maybe better?

Change-Id: I669c67e83acf1b749bfb534d3b3c0915c129d686

* All three methods work.

Change-Id: If77074fa43f6420d1ec9b594fe366415f5a41f2c

* Fix hitting hardware triggers with `-rtos riscv`.

Change-Id: I8d4600e1c66fa0e3b9d986b96a5973d09f40735c

* Fix halting dual core E31.

Change-Id: Ic2d885e027312b68e2f3c6854957fbfee09f814b

* Not addressing this TODO right now.

Change-Id: Ic7c0d32424068ae1de04d37d15a411c1957207c4

* Remove duplicate line.

Change-Id: I14fe8d422f23c97afdaa20a02c0e3ab568219467
2019-05-09 11:32:04 -07:00
Greg Savin 5190dd4cef
Support for driving RISC-V DM via Arty's own JTAG chain using BSCAN tunnel (#370)
Including adjustments in response to review comments.
2019-04-23 16:25:22 -07:00
Marc Schink d5936dc688 target/riscv: Free registers to avoid memory leak
Tested with SiFive HiFive1 development board.

Change-Id: I96a9a528057fcf9fc54d3da46a672d2cd54c3d5f
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4885
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-10 16:37:21 +01:00
Antonio Borneo 69ba2a677b target/riscv: use coherent syntax in struct initialization
While initializing struct command_registration, the field's name "name"
is not specified, thus relying on the fact that it is the first field
declared in the struct and it's initialization value can be listed as
the first one.

Be coherent in the struct initialization and always use the field's
name.

Change-Id: Iefaeb15cc051db9f1e0f0140fe2f231b45f5bb12
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5013
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2019-04-07 08:14:50 +01:00
Tim Newsome 79f9672615 Merge branch 'master' into from_upstream
Conflicts:
	src/flash/nor/at91sam4.c
	src/flash/nor/at91sam4l.c
	src/flash/nor/at91samd.c
	src/flash/nor/ath79.c
	src/flash/nor/atsame5.c
	src/flash/nor/cfi.c
	src/flash/nor/core.c
	src/flash/nor/fespi.c
	src/flash/nor/kinetis.c
	src/flash/nor/kinetis_ke.c
	src/flash/nor/lpc2000.c
	src/flash/nor/niietcm4.c
	src/flash/nor/nrf5.c
	src/flash/nor/numicro.c
	src/flash/nor/pic32mx.c
	src/flash/nor/stm32h7x.c
	src/flash/nor/stm32lx.c
	src/flash/nor/stmsmi.c
	src/flash/nor/tcl.c
	src/flash/nor/tms470.c
	src/flash/nor/virtual.c
	src/flash/nor/xmc4xxx.c
	src/rtos/hwthread.c
	src/rtos/rtos.c
	src/server/gdb_server.c
	src/target/riscv/riscv-011.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h

Change-Id: I9f0f373d45a9e5845bca83ca52e977f727ea4425
2019-04-03 12:38:27 -07:00
Tim Newsome c089e6ae9a
Support simultaneous resume using hasel (#364)
* Remove unnecessary 0.11 code.

Don't need need_strict_step anymore now that we have
riscv_hit_watchpoint().

Don't need 32-bit warning in riscv011_resume() now that address is a
target_address_t.

Change-Id: I375c023a7ec9f62d80b037ddb64d14526ba0a3dc

* WIP little refactor working towards hasel support.

Change-Id: Ie0b8dfd9e5ae2e36613fa00e14c3cd32749141bf

* More refactoring.

Change-Id: I083387c2ecff78ddfea3ed5078444732d77b909b

* More refactoring.

Change-Id: Icea1308499492da51354f89e1529353e8385f3a1

* Starting to work towards actual hasel changes.

Change-Id: If0df05ffa66cc58400b4855f9630a8b1bae3030e

* Implement simultaneous resume using hasel.

Change-Id: I97971d7564fdb159d2052393c8b82a2ffaa8833f

* Add support back for targets that don't have hasel.

Change-Id: I6d5439f0615d5d5333127d280e4f2642649a119a

* Make hasel work with >32 harts.

Change-Id: I3c55009d48bfc5dd62e3341df4e4bd21df2fe44f
2019-04-03 12:13:09 -07:00
Tim Newsome bc72695f67 Lots of RISC-V improvements.
This represents months of continuing RISC-V work, with too many changes
to list individually. Some improvements:
* Fixed memory leaks.
* Better handling of dbus timeouts.
* Add `riscv expose_custom` command.
* Somewhat deal with cache coherency.
* Deal with more timeouts during block memory accesses.
* Basic debug compliance test.
* Tell gdb which watchpoint hit.
* SMP support for use with -rtos hwthread
* Add `riscv set_ir`

Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4922
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-03-27 08:53:09 +00:00
Tim Newsome 57e30102ea gdb_server, target: Add target_address_bits()
Targets can use this to expose how many address bits there are.
gdb_server uses this to send gdb the appropriate upper limit in the
memory-map. (Before this change the upper limit would only be correct
for 32-bit targets.)

Change-Id: Idb0933255ed53951fcfb05e040674bcdf19441e1
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4947
Tested-by: jenkins
Reviewed-by: Peter Mamonov <pmamonov@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-03-08 14:05:19 +00:00
Tim Newsome e96f4b1b06 Fix old cut and paste bug.
Change-Id: Id06fb98ed3dd1b3987e4eafa0ec271c1cd77fef6
2019-02-11 14:04:21 -08:00
Tim Newsome 1c6d52cd88 Merge branch 'master' into from_upstream
Conflicts:
	README
	contrib/loaders/flash/fespi/Makefile
	src/flash/nor/fespi.c
	src/flash/nor/spi.c

Change-Id: I78a4e73685cc95daace95e9d16066a6fb51034fb
2019-02-08 14:39:47 -08:00
Tim Newsome 80ef54dba2
Rtos riscv (#350)
* Implement riscv_get_thread_reg().

This is necessary because riscv_get_gdb_reg_list() now reads all
registers, which ended up causing `-rtos riscv` to read all registers
whenever one was requested (because the register cache is wiped every
time we switch to a different hart).

CustomRegisterTest went from 1329s to 106s.

Change-Id: I8e9918b7a532d44bca927f67aae5ac34954a8d32

* Also implement riscv_set_reg().

Now all the `-rtos riscv` tests pass again, at regular speed.

Change-Id: I55164224672d9dcc9eb4d1184b47258ff3c2cff1

* Better error messages.

Change-Id: I4125f9a54750d9d0ee22c4fa84b9dd3f5af203f5

* Add target_get_gdb_reg_list_noread().

Being explicit about what's expected gets `-rtos riscv` back to `-rtos
hwthread` time.

Change-Id: I6e57390c2fe79b5e6799bfda980d89697e2e29f7

* Revert a change I made that has no effect.

I don't understand exactly what all this test protects against, and I
shouldn't change it unless I do.

Change-Id: Ib329d4e34d65d2b38559b89b7afb3678f439ad2c
2019-02-07 13:24:44 -08:00
Tomas Vanek 7a3eec2b4d target algo: do not write reg_param if direction is PARAM_IN
Without this change xxx_start_algorithm() writes all register
parameters no matter of their direction. It usually results
in writing of uninitialized reg_params[].value - possibly
reported by valgrind.

While on it fix the wrong parameter direction in
kinetis_disable_wdog_algo(). This bug did not have any
impact because of unconditional write of reg_params.

Change-Id: Ia9c6a7b37f77d5eb6e5f5463012dddd50471742b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4813
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-02-07 07:51:50 +00:00
Tim Newsome e186f62962 More cleanup.
Change-Id: I804bdcec23b69d77dfc376e23c6d1f29f99e7335
2019-01-25 15:31:42 -08:00
Tim Newsome 96df1db7b1 Remove debug statements.
Change-Id: If37bc883fea0b83740bfd6a7fcb2091db0ac61f0
2019-01-25 14:48:22 -08:00
Tim Newsome 49dd7ded87 Merge branch 'riscv' into hwthread 2019-01-25 14:17:32 -08:00
Tim Newsome 82cf37d36c Invalidate register cache on reset.
All tests pass with `-rtos hwthread` against spike32!

Change-Id: I9051259d2702c76b7c35aeffeac020a773e0597a
2019-01-25 13:11:06 -08:00
Tim Newsome afedcb337a WIP on hardware breakpoints.
This is messy, but contains at least some bugfixes.

39/43 tests pass now.

Change-Id: Ic9e8dad2a0ceb237e28c93906d1cd60876a5766d
2019-01-24 15:27:53 -08:00
Tim Newsome c296c62521 Halt all SMP harts on halt request.
38/45 tests pass.

Change-Id: Ia4fd523139c197020d9277be4bf5f92079520068
2019-01-18 13:18:15 -08:00
Tim Newsome c1ef5f61c3 Fix reading of non-general registers for hwthread
Previously the code made the assumption (which is valid for conventional
RTOSs) that special registers (e.g. CSRs) are the same across threads.

26/45 tests pass.

Change-Id: Ibb3398790d7354a995d506772375d869f608f1f0
2019-01-17 15:01:47 -08:00
Tim Newsome 02ece46105 Clean up register caching a little.
Change-Id: Id039aedac44d9c206ac4bd30eb3ef754e190c3fe
2019-01-10 12:32:03 -08:00
Darius Rad 00b591a09a Add 'riscv set_ir' command to set IR value for JTAG registers.
This allows using different TAP addresses, for example, if using
BSCANE2 primitives on a Xilinx FPGA.
2019-01-09 17:20:39 -05:00
Tim Newsome e6b6aa615b Add comment for reset_delays_wait.
Also refactor so there's just one of them in riscv, instead of one for
0.11 and one for 0.13.

Change-Id: I0dbbf112b4c57f76bed971a22dadf844fa27cd4e
2019-01-08 14:01:25 -08:00
Tim Newsome fd49f5e967 Make riscv_get_gdb_reg_list read the registers.
This may not be the correct behavior, but it gets me further through the
tests.

Change-Id: I6e9b77e927700de706b6ece723f4d530fa566761
2019-01-07 12:17:41 -08:00
Tim Newsome a9d436e77f WIP make riscv work with -rtos hwthread.
Change-Id: I37bb16291fa87a83f21e5fd8bad53492a4d69425
2019-01-03 15:06:35 -08:00
Tim Newsome 41e5272adc Add `riscv reset_delays` for testing.
This allows me to test corner cases in block read/write errors.

Change-Id: I3ccfe707851dbc578277ea0d5e278eab81a3c7ef
2018-12-04 12:38:51 -08:00
Tim Newsome d18c2f23d3
Doxygen style, too. (#325)
* Doxygen style, too.

Change-Id: I85e60e8577c4177ac7094ae41ee84357b292a89c

* More Doxygen.

Change-Id: Ic7477dce5459146f299e080cac1a3f133af7abdb
2018-11-07 13:53:52 -08:00
Tim Newsome 874cadca31
Conform to OpenOCD style. (#323)
Change-Id: I11b5b66e474d3e1d979b4db537363d025f8e2c9a
2018-11-05 12:27:56 -08:00
Pavel S. Smirnov 60368dd62e FIX(src/target/riscv/riscv.c): riscv_add_breakpoint: RVC: invalid 32bit transactions size for 16bit aligned instruction (#322) 2018-11-05 11:34:44 -08:00
Carsten Gosvig dc4fe85880 Old fixes from June (#311)
* Changed logging level

* Added logging statement

* Removed halt event when attaching to target

* Extended some packet handling

* Extended handling of rtos_hart_id and clearing of register cache

* Extended execute_fence to handle all harts

* Removing logging statement again

* Updated according to review comments

* Forgot to re-add the return statement

* Was removing too much for the if statement to work

* This needs to >= 3 now to handle both a fence and a fence.i
2018-10-30 11:29:00 -07:00
Tim Newsome e54511ffa4
Revert "Don't report exact watchpoint to gdb. (#300)" (#304)
This reverts commit 933cb875a8.

https://github.com/riscv/riscv-openocd/issues/295 was fixed in gdb.
2018-10-24 13:02:44 -07:00