The command 'cache auto' was introduced with commit cd440bd32a
("add armv7a_cache handlers") in 2015 to allow disabling the cache
handling done automatically by OpenOCD.
This was probably a way to test the cache handling when there were
still the two independent accesses for APB-AP CPU debug and for
AHB-AP memory bus.
The handling of cache for cortex_a is robust and there is no more
reason to disable it.
The command 'cache auto' is not used in any upstream script.
On target aarch64 this command has never been introduced as the
cache is always handled automatically by OpenOCD.
Drop the command 'cache auto' and add it in the deprecated list.
Drop the flag 'auto_cache_enabled' by considering it as true.
Rename the function 'armv7a_cache_auto_flush_all_data()' as
'armv7a_cache_flush_all_data()' and, while there, fix the error
propagation in SMP case.
Change-Id: I0399f1081b08c4929e0795b76f4a686630f41d56
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8230
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
The initial OpenOCD code for Cortex-A (ARMv7a) [1] was merged in
2009 but, due to lack of public documentation for ARMv7a, it was
almost a simple copy/paste from the existing code for Cortex-M
(ARMv7m).
On Cortex-M the same AP provides access to both CPU debug and CPU
memory. This feature is not present on ARMv7a.
To still keep some communality with ARMv7m code, the change [2]
splits the CPU debug access from the CPU memory access by using
two independent AP; this is copied from the system architecture of
TI OMAP3530 which provides to DAP a direct AHB-AP memory bus on
AP#0, separated from AP#1 for the APB-AP CPU debug.
But the direct memory access through the system bus breaks the
coherency between memory and CPU caches, so change [3] added some
cache invalidation to avoid issues.
The code to allow ARMv7a CPU to really read/write in CPU memory
was added by change [4] in 2011. Such still not optimized
implementation was very slow, so it did not replace the access
through the system bus. A selection through DAP's 'apsel" command
was used to select between the two modes.
Only in 2015, with change [5], the speed of CPU read/write was
improved using the DCC_FAST_MODE. But the direct access to the
memory through the system bus remained.
Finally, with change [6] in 2018 the system bus access was dropped
for good, as the new virtual target "mem_ap" could implement such
access in a more clean way.
Only memory access through CPU remained for ARMv7a.
Nevertheless, a useless cache invalidation remained in the code,
decreasing the speed of the write access.
Drop the useless cache invalidate on CPU memory write and the
associated comment, not anymore valid.
Drop the now unused function armv7a_cache_auto_flush_on_write().
This provides a speedup of between 4 and 8, depending on adapter
and JTAG/SWD speed.
Link: [1] 7a93100c2d ("Add minimalist Cortex A8 file")
Link: [2] 1d0b276c9f ("The rest of the Cortex-A8 support from Magnus: ...")
Link: [3] d4e4d65d28 ("Cache invalidation when writing to memory")
Link: [4] 05ab8bdb81 ("cortex_a9: implement read/write memory through APB-AP")
Link: [5] 0228f8e827 ("Cortex A: fix extra memory read and non-word sizes")
Link: [6] fac9be64d9 ("target/cortex_a: remove buggy memory AP accesses")
Change-Id: Ifa3c7ddf2698b2c87037fb48f783844034a7140e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8229
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Replace the FSF boilerplate with the SPDX tag.
The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.
Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7071
Tested-by: jenkins
Modify the format strings to properly handle uint32_t data types.
While there, fix prototype mismatch between header and C file of
the function armv7a_l1_d_cache_inval_virt().
Change-Id: I434bd241fa5c38e0c15d22cda2295097050067f5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5818
Tested-by: jenkins
Also make GPL notices consistent according to:
https://www.gnu.org/licenses/gpl-howto.html
Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3488
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint,
to make sure the d-cache is clean and invalid at the breakpoint
location down to PoC.
Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint
again, so that d-cache will pick up the modified code.
Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint
to memory to make the change visible to the CPU.
Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3033
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
The following changes are implemented:
- Clean&Invalidate the VA range to PoC *before* the write takes place
- Remove SMP handling since DCCIMVA instruction already maintains SMP
coherence.
- Remove separate Invalidate step
Change-Id: I19fd3cc226d8ecf2937276fc63258b6a26e369a7
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3027
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
This patch adds a function for cleaning & invalidating a virtual
address range from the architecture caches down to the point of
coherence.
Change-Id: I4061ab023a3797fabc967f3a34498034841d52c6
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3026
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
ARMv7 architecture allows up to 7 cache levels that are architecturally
visible, as opposed to "system caches", which are outside of the domain
defined by ARMv7 and require separate management. This patch enables
detection and identification of caches at all levels. It also implements
a new "flush-all" function that cleans & invalidates all cache levels to
the "Point of Coherence".
Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3024
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
This patch introduces, new command set and handlers for l1 and l2x caches.
Patch set 10 folded the following changes into this one:
Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415
If8d87a03281d0f4ad402909998e7834eb4837e79
I0749f129fa74e04f4e9c20d143a744f09ef750d8
Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/2800
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Antonio Borneo
Marc Schink
Matthias Welwarsky
Oleksij Rempel