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5 Commits

Author SHA1 Message Date
elmot eb26a884e0 config: stm32l01x and stm32l02x chips support 
New low-end chips have only 2k of RAM, workarea size adjusted

Change-Id: Ibfccd73fef9e6dabffc87d901736c5626ce411fe
Signed-off-by: Ilia Motornyi <elijah.mot@gmail.com>
Reviewed-on: http://openocd.zylin.com/4308
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
 2017-12-08 14:59:22 +00:00
Uwe Bonnes 49cac156bb stm32l0.cfg: Add examine-end event like on other STM32 targets. 
Enable debug in standby/stop/sleep.
Stop watchdogs during halt.

Change-Id: I8383a191cd897118bd88bf78528d05943f3a368e
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3882
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
 2016-12-08 17:09:47 +00:00
Paul Fertser a1bbf4b75b cfg: add srst_nogate to the supported targets, remove from board configs 
It depends on the particular target whether it can work with SRST
asserted or not, so this belongs to the target config rather than the
board config.

Also, this allows for simple

openocd -f myboard.cfg -c "reset_config connect_assert_srst"

command to be used whenever a user feels a need to connect to an
unresponsive target.

Change-Id: I3d8da9ae47088fc0c75a20bfdd20074be1014de0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2459
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
 2015-01-26 20:54:51 +00:00
Karl Palsson 1663a17d9d target/stm32xx: Endian is not configurable. 
So remove it from all the configs, it's misleading, and leads to cargo
culting of config files.

Change-Id: I2b77e60d5e96f9759c7c9fc91b20e73be2e95d9a
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2446
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
 2015-01-15 23:26:18 +00:00
Karl Palsson c3ec1940b5 stm32l: split l0/l1 support no jtag, different HSI settings 
L0 is cortex m0+, so different id codes, SWD only, different addresses
for the clock speedup.  It has no endian options, no boundary scan.

Removed all L0 specific portions from L1 files, and renamed files to clarify
their purpose.  The deprecated stm32lx_stlink.cfg is kept as is, as it is only
around for backwards compatibility with prior releases.

Tested on STM32L053 Discovery and STM32L151 Discovery.

Has _not_ been tested with jtag on L1.

Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2405
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
 2014-12-03 09:10:21 +00:00